• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.219-225
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• 2013

Program and erase characteristics of the elliptic gate all around (e-GAA) SONOS cell have been studied as the variation of eccentricity of the channel. An analytic program and erase model for the elliptic GAA SONOS cell is proposed and evaluated. The model shows that the ISPP (incremental-step-pulse programming) property is changed non-linearly as the eccentricity of the e-GAA SONOS cell is increased. It is differently from the well known linear relationship for that of 2D SONOS and even 3D circular SONOS cell with program bias. We can find that the simulation results of ISPP characteristics are in accord with the experimental data.

• Transactions on Electrical and Electronic Materials
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• v.2 no.4
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• pp.1-6
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• 2001

In this paper, a 1.5 V high-gain high-frequency CMOS complementary operational amplifier is presented. The input stage of op-amp is designed for supporting the constant transconductance on the Input stage by consisting of the parallel-connected rail-to-rail complementary differential pairs. And consisting of the class-AB rail-to-rail output stage using the concept of elementary shunt stage and the grounded-gate cascode compensation technique for improving the low PSRR which was a disadvantage in the general CMOS complementary input stage, the load dependence of open loop gain and the stability of op- amp on the output load are improved, and the high-gain high-frequency operation can be achieved. The designed op-amp operates perfectly on the complementary mode with the 180° phase conversion for a 1.5 V supply voltage, and shows the DC open loop gain of 84 dB, the phase margin of 65°, and the unity gain frequency of 20 MHz. In addition, the amplifier shows the 0.1 % settling time of .179 ㎲ for the positive step and 0.154 ㎲ for the negative step on the 100 mV small-signal step, respectively, and shows the total power dissipation of 8.93 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.125-136
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• 2009

This paper presents a high-speed low-complexity two-bit level pipelined Viterbi decoder architecture for MB-OFDM UWB systems. As the add-compare-select unit (ACSU) is the main bottleneck of the Viterbi decoder, this paper proposes a novel two-bit level pipelined MSB-first ACSU, which is based on 2-step look-ahead techniques to reduce the critical path. The proposed ACSU architecture requires approximately 12% fewer gate counts and 9% faster speed than the conventional MSB-first ACSU. The proposed Viterbi decoder was implemented with $0.18-{\mu}m$ CMOS standard cell technology and a supply voltage of 1.8V. It operates at a clock frequency of 870 MHZ and has a throughput of 1.74 Gb/s.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.6
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• pp.235-240
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• 2003

In this paper, we present the fabrication and the characteristic analysis of sequential lateral solidification(SLS) poly-Si thin film transistors(TFT's) with molybdenum gate for active matrix liquid displays (AMLCD's) pixel controlling devices. The molybdenum gate is applied for the purpose of low temperature processing. The maximum processing temperature is 55$0^{\circ}C$ at the dopant thermal annealing step. The SLS processed poly-Si film which is reduced grain and grain boundary effect, is applied for the purpose of electrical characteristics improvements of poly-Si TFT's. The fabricated low temperature SLS poly-Si TFT's had a varying the channel length and width from 10${\mu}{\textrm}{m}$ to 2${\mu}{\textrm}{m}$. And to analyze these devices, extract electrical characteristic parameters (field effect mobility, threshold voltage, subthreshold slope, on off current etc) from current-voltage transfer characteristics curve. The extract electrical characteristic of fabricated low temperature SLS poly-Si TFT's showed the mobility of 100~400cm$^2$/Vs, the off current of about 100pA, and the on/off current ratio of about $10^7$. Also, we observed that the change of grain boundary according to varying channel length is dominant for the change of electrical characteristics more than the change of grain boundary according to varying channel width. Hereby, we comprehend well the characteristics of SLS processed poly-Si TFT's witch is recrystallized to channel length direction.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.2
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• pp.111-115
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• 2001

Metamorphic InAlAs/InGaAs HEMT are successfully demonstrated, exhibiting several advantages over conventional P-HEMT on GaAs and LM-HEMT on InP substrate. The strain-relaxed metamorphic structure is grown by MBE on the GaAs substrate with the inverse-step graded InAlAs metamorphic buffer. The device with 40% indium content shows the better characteristics than the device with 53% indium content. The fabricated metamorphic HEMT with $0.2\mu\textrm{m}$T-gate and 40% indium content shows the excellent DC and microwave characteristics of $V_{th}-0.65V,{\;}g_{m,max}=620{\;}mS/mm,{\;}f_T120GHZ{\;}and{\;}f_{max}=210GHZ$.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.185-190
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• 2003

고유전물질인 $HfO_2$ 극박막에 사용될 TaN metal 전극에 대한 특성에 대한 연구를 하였다. 고유전물질인 $HfO_2$는 4" p-type wafer를 SCI cleaning후 ALD(atomic layer deposition)을 통해 $50\AA$를 증착하였다. Ff source는 TEMAH를 이용하였으며 Oxygen source는 $H_2O$를 이용하였다. 이렇게 증착한 $HfO_2$ 극박막에 Ta target을 이용하여 질소 가스를 Ar가스에 첨가하여 reactive sputtering을 통해서 TaN 전극을 증착하였다. TaN 박막의 증착두께는 a--step과 TEM을 통해서 확인하였으며 면저항은 four point probe를 이용하여 측정하였다. 이렇게 증착된 $HfO_2/TaN$구조에 대한 전기적 특성을 측정하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.11
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• pp.1001-1006
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• 2005

A new fabrication method is proposed to form the stacked polysilicon gate by nitridation in $N_2$ atmosphere using conventional LP-CVD system. Two step stacked layers with an amorphous layer on top of a polycrystalline layer as well as three step stacked layers with polycrystalline films were fabricated using the proposed method. SIMS profile showed that the proposed method would successfully create the nitrogen-rich layers between the stacked polysilicon layers, thus resulting in effective retardation of dopant diffusion. It was observed that the dopants in stacked films were piled-up at the interface. TEM image also showed clear distinction of stacked layers, their plane grain size and grain mismatch at interface layers. Therefore, the number of stacked polysilicon layers with different crystalline structures, interface position and crystal phase can be easily controlled to improve the device performance and reliability without any negative effects in nano-scale CMOSFETs.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.185-188
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• 2001

In this study, $Al_2$O$_3$films have been deposited with Atomic Layer Deposition(ALD) for gate insulator for MPTMA and $H_2O$ at low temperature below 40$0^{\circ}C$ . Conventional methods of $Al_2$O$_3$thin film deposition have suffered from the poor step coverage due to reduction of device dimension and increasing contact/via hole aspect ratio. ALD is a self-limiting growth process with controlled surface reaction where the growth rate is only dependent on the number of growth cycle and the lattice parameter of materials. ALD growth process has many advantages including accurate thickness control, large area and large batch capability, good uniformity, and pinholes freeness.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.10
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• pp.1157-1162
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• 2007

In this paper, E-TDLNN(Expanded-Tapped Delay Line Neural Network) method is suggested to make the model of power amplifier effectively. This method is the one for making the model of power amplifier through the study in neural network to the target value, the measured output spectrum of power amplifier, after adding the external value factor, gate bias, as an invariant input to the TDLNN method which suggested the memory effect of power amplifier effectively. To prove the validity of suggested method, the data at 2 points, 3.45 V and 3.50 V of gate bias range $3.4{\sim}3.6V$ with the 0.01 V step change, are studied and the predicted results at the gate bias 3.40 V, 3.48 V, 3.53 V and 3.60 V shows good coincidence with the measured values.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.10
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• pp.41-50
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• 1993

This paper describes the fabrication process and electrical characteristics of PSA (Polysilicon Self-Align) bipolar transistors with a thin base width of 1100.angs.. To realize this shallow junction depth, one-step rapid thermal annealing(RTA) technology has been applied instead of conventional furnace annealing process. It has been shown that the series resistances and parasitic capacitances are significantly reduced in the device with emitter area of 1${\times}4{\mu}m^{2}$. The switching speed of 2.4ns/gate was obtained by measuring the minimum propagation delay time in the I$^{2}$L ring oscillator with 31 stages.