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High-Speed Low-Complexity Two-Bit Level Pipelined Viterbi Decoder for UWB Systems  

Goo, Yong-Je (School of Information and Communication Engineering, Inha University)
Lee, Han-Ho (School of Information and Communication Engineering, Inha University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.8, 2009 , pp. 125-136 More about this Journal
Abstract
This paper presents a high-speed low-complexity two-bit level pipelined Viterbi decoder architecture for MB-OFDM UWB systems. As the add-compare-select unit (ACSU) is the main bottleneck of the Viterbi decoder, this paper proposes a novel two-bit level pipelined MSB-first ACSU, which is based on 2-step look-ahead techniques to reduce the critical path. The proposed ACSU architecture requires approximately 12% fewer gate counts and 9% faster speed than the conventional MSB-first ACSU. The proposed Viterbi decoder was implemented with $0.18-{\mu}m$ CMOS standard cell technology and a supply voltage of 1.8V. It operates at a clock frequency of 870 MHZ and has a throughput of 1.74 Gb/s.
Keywords
Vitrbi decoder; radix-4; multiband orthogonal frequency-division multiplexing (MB-OFDM); ultra wide band (UWB);
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