• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.673-681
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• 2014

In this paper, a novel low specific on-resistance SOI LDMOS Device with P+P-top layer in the drift region is proposed and investigated using a two dimensional device simulator, MEDICI. The structure is characterized by a heavily-doped $P^+$ region which is connected to the P-top layer in the drift region. The $P^+$ region can modulates the surface electric field profile, increases the drift doping concentration and reduces the sensitivity of the breakdown voltage on the geometry parameters. Compared to the conventional D-RESURF device, a 25.8% decrease in specific on-resistance and a 48.2% increase in figure of merit can be obtained in the novel device. Furthermore, the novel $P^+P$-top device also present cost efficiency due to the fact that the $P^+$ region can be fabricated together with the P-type body contact region without any additional mask.

• 대한전자공학회논문지SD
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• 제38권1호
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• pp.1-12
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• 2001

2차원 소자 시뮬레이터를 이용하는 혼합모드 과도해석을 통해, NMOS 트랜지스터를 ESD 보호용 소자로 사용하는 CMOS 칩에서의 HBM ESD 현상에 대한 과도해석 방법론을 제시하고 HBM 방전 미케니즘에 대해 상세히 분석하였고, 보호용 소자 내에서의 2차항복 현상을 성공적으로 시뮬레이션하여 소자 파괴에 이르는 미케니즘을 설명하였다., 보호용 소자 구조의 변화가 방전 특성에 미치는 영향을 조사하기 위해 DC 해석 결과와 혼합모드 과도해석 결과를 비교 분석하였고, 분석 결과를 근거로 하여 HBM ESD에 보다 견고한 보호용 소자의 구조 설계에 대해 논의하였다.

• 전자공학회논문지D
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• 제35D권6호
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• pp.37-45
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• 1998

본 논문에서는 본 연구진이 개발 중인 INPROS 3차원 반도체 공정 시뮬레이터 시스템에 이온주입된 불순물의 과도 확산(TED, transient enhanced diffusion) 기능을 첨가하여 수행한 계산 결과를 발표한다. 실리콘 내부에 이온주입된 불순물의 재분포를 시뮬레이션하기 위하여, 먼저 몬테카를로 방법으로 이온주입 공정을 수행하였고, 유한요소법을 이용하여 확산 공정을 수행하였다. 저온 열처리 공정에서의 붕소의 과도 확산을 확인하기 위하여, 에피 성장된 붕소 에피층에 비소와 인을 이온 주입시킨 후, 750℃의 저온에서 2시간 동안 열처리 공정을 수행하였다. 3차원 INPROS 시뮬레이터의 결과와 실험적으로 측정한 SIMS 데이터와 그 결과가 일치함을 확인하였다. INPROS의 점결함 의존성 과도 증속 확산 모델과 소자 시뮬레이터인 PISCES를 이용하여 역 단채널 길이 효과(RSCE, reverse short channel effect)를 시뮬레이션하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 추계학술대회 논문집
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• pp.40-45
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• 1994

The TCAD(Technology Computer Aided Design) software tool is a popular name to be able to simulate the semiconductor process and device circuit. We have developed a two-dimensional TCAD software tool included an editor, parser, each process unit, and 2D, 3D graphic routine that is Integrated Environment. The initial grid for numerical analysis is automatically generated with the geometric series that use the user default(given) line and position separated with grid interval and the nodes corresponding to each mesh point stoic the all the possible attribute. Also, we made a data structure called PIF for input or output. Methods of ion implantation in this paper arc Monte Carlo, Gaussian Pearson and Dual-Pearson. Analytical model such as Gaussian, Pearson and Dual-Pearson were considered the multilayer structure and two-dimensional tilted implantation. We simuttaneously calculated the continuity equation of impurity and point defect in diffusion simulation. Oxidation process was simulated by analytical ERFC(Complementary Error Function) model for local oxidation.

• 한국전기전자재료학회논문지
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• 제23권6호
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• pp.436-439
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• 2010

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics. In this work, we report the effect of the interface states ($Q_f$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized by using a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. When the $SiO_2$/SiC interface charge decreases, power losses and switching time also decrease, primarily due to the lowered channel mobilities. High density interface states can result in increased carrier trapping, or more recombination centers or scattering sites. Therefore, the quality of $SiO_2$/SiC interfaces has a important effect on both the static and transient properties of SiC MOSFET devices.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권2호
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• pp.110-119
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• 2007

A new two-dimensional analytical model for dual-material double-gate fully-depleted SOI MOSFET with Pearson-IV type Doping Distribution is presented. An investigation of electrical MOSFET parameters i.e. drain current, transconductance, channel resistance and device capacitance in DM DG FD SOI MOSFET is carried out with Pearson-IV type doping distribution as it is essential to establish proper profiles to get the optimum performance of the device. These parameters are categorically derived keeping view of potential at the center (${\phi}_c$) of the double gate SOI MOSFET as it is more sensitive than the potential at the surface (${\phi}_s$). The proposed structure is such that the work function of the gate material (both sides) near the source is higher than the one near the drain. This work demonstrates the benefits of high performance proposed structure over their single material gate counterparts. The results predicted by the model are compared with those obtained by 2D device simulator ATLAS to verify the accuracy of the proposed model.

• 전기전자학회논문지
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• 제11권4호
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• pp.235-238
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• 2007

2차원 소자 시뮬레이터인 TMA 메디치를 이용하여 필드링와 깊은 접합 필드링에 대해 연구하였다. 이온 주입될 위치를 미리 트랜치 식각을 시킴으로써 항복전압 특성을 향상시킬 수 있었다. 시뮬레이션 결과 기존 필드링의 항복전압대비 깊은 접합 필드링 항복전압은 약 30%의 증가를 보였다. 깊은 접합 필드링은 같은 면적을 차지하는 조건하에서 설계 및 제작이 비교적 용이하고, 표면 전하의 영향도 적은 것으로 나타났다. 본 논문에서는 여러 분석을 통해 깊은 접합 필드링의 향상된 특성을 논하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 춘계학술대회 논문집
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• pp.168-171
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• 1997

TFT2DS was developed to provide the usefulness as an analytic and design tool. The static characteristics of a-Si:H TFTs demonstrated a good agreement between simulated and measured data. This paper shows that TFT2DS can optimize the physical parameters of a-Si:H through sensitivity simulations and compute the static characteristics of a-Si:H TFTs. Moreover, through the sensitivity study of the parameters, it is shown that the optimizations of both the physical parameters of a-Si:H and the parameters of a-Si:H deposition, which must be inter-related, might be possibl.

• Journal of Electrical Engineering and Technology
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• 제7권2호
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• pp.236-239
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• 2012

In this paper, we study the transient characteristics of 4H-SiC DMOSFETs with different interface charges to improve the turn-on rising time. A physics-based two-dimensional mixed device and circuit simulator was used to understand the relationship between the switching characteristics and the physical device structures. As the $SiO_2$/SiC interface charge increases, the current density is reduced and the switching time is increased, which is due primarily to the lowered channel mobility. The result of the switching performance is shown as a function of the gate-to-source capacitance and the channel resistance. The results show that the switching performance of the 4H-SiC DMOSFET is sensitive to the channel resistance that is affected by the interface charge variations, which suggests that it is essential to reduce the interface charge densities in order to improve the switching speed in 4H-SiC DMOSFETs.

• 대한전자공학회논문지SD
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• 제39권10호
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• pp.1-8
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• 2002

C-V 방법은 소형화된 MOSFET에서 effective channel length(L/sub eff/)를 추출하기 위한 방법 중 한가지이다. 이 방법은 critical gate bias point에서 channel length에 영향을 받지 않는 extrinsic overlap 영역의 길이(△L)를 구하여 L/sub eff/를 추출하게 된다.본 논문에서는 서로 다른 두 개의 C-V 방법에 대해 실험을 수행하였다. 그리고 실험으로 추출한 값과 2차원 소자 시뮬레이터의 결과를 비교하여 C-V 방법의 정화도를 분석하였다.