• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.68-74
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• 2010

A sub-${\mu}$W CMOS Wien-Bridge oscillator for ultra low power (ULP) radio applications is presented. The Wien-Bridge oscillator is based on an non-inverting opamp amplifier with a closed-loop gain $1+R_2/R_1$ as a means of providing necessary loop gain. An additional RC network provides appropriate phase shift for satisfying the Barkhausen oscillation condition at the given frequency of 1/($2{\pi}RC$). In this design, we propose a novel loop gain control method based on a variable capacitor network instead of a rather conventional variable resistor network. Implemented in $0.18{\mu}m$ CMOS, the oscillator consumes only 560 nA at the oscillation frequency of 22 kHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.912-920
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• 2003

This paper is about the design of a small wide-band slot loop antenna, which consists of dual offset-fed and rectangular loop within the slot on a substrate. The proposed antenna is a novel structure generating a multi-resonances due to three geometrical resonance structures. The impedance matching of this antenna can be accomplished by changing the offset position of dual-fed at resonance frequencies. In this experiment, the slot of a fabricated antenna has a center frequency of 6.755㎓, 12.5mm${\times}$50mm in size and the rectangular loop has 10.5mm${\times}$27.5mm in size. The measured result is fractional bandwidth 63.21% with VSWR 2:1, which is agreed with the simulated result within 5% of error, and the maximum antenna gain is 7.42㏈i.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2409-2418
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• 2013

Two frequency synthesizers are proposed to generate a clock for a sub-sampler of an on-chip oscilloscope in this paper. These proposed frequency synthesizers are designed by using a multi-phase delayed-locked loop (DLL)-based phase selector and a fractional-N phase-locked loop (PLL), and they are analyzed by comparing simulation results of each frequency synthesizer. Two proposed frequency synthesizers are designed using a 65-nm CMOS process with a 1V supply and output the clock with the frequency of 121.15 MHz when the frequency of an input clock is 125 MHz. The designed frequency synthesizer using a multi-phase DLL-based phase selector has the area of 0.167 $mm^2$ and the peak-to-peak jitter performance of 2.88 ps when it consumes the power of 4.75 mW. The designed frequency synthesizer using a fractional-N PLL has the area of 0.662 $mm^2$ and the peak-to-peak jitter performance of 7.2 ps when it consumes the power of 1.16 mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1552-1558
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• 2011

In this paper, a dual-loop Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a low power consuming voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF which occupies a large area. The proposed dual-loop P DLL can have a small gain VCDL by controlling the magnitude of capacitor and charge pump current on the loop of VCDL. The proposed dual-loop P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by Hspice simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.37-44
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• 2009

A novel phase-locked loop(PLL) architecture with resistance and capacitance scaling scheme has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. This architecture makes it possible to have a narrow bandwidth and low resistance in the loop filter, which improves phase noise and reference spur characteristics. It has been fabricated with a 3.3V $0.35{\mu}m$ CMOS process. The measured locking time is $25{\mu}s$ with the measured phase noise of -105.37 dBc/Hz @1MHz and the reference spur of -50dBc at 851.2MHz output frequency

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.281-281
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• 2010

ITER 블랑켓 시험모듈(TBM)의 액체형 증식재 성능 시험용 루프의 설계를 완료하였고 현재시험용 루프를 제작 및 설치중이다. 액체형 증식재 성능 시험용 루프의 핵심 구성 부품인 액체 저장용 탱크, 전자석, EM 펌프들과 이들 장치들의 전원장치 및 제어장치를 제작 완료하였다. 액체형 증식재 성능 시험용 루프 설치를 위한 데크를 제작하였으며, 제작된 실험 데크의 총 지지하중은 10 톤 이상이다. 루프설치대 위에 성능 시험용 루프가 설치되며 루프 설치대는 $3\;m\;{\times}\;2.4\;m$ 의 직사각형으로 제작되었으며, 실험 종료 및 유지 보수 시 액체증식재의 drain을 고려하여 전체 루프는 각도 조절이 가능하도록 제작되었다. 루프내의 유량을 측정하기 위한 유량계, 전자석 자장의 변화에 따른 압력의 변화를 측정하기 위한 차압센서가 전자석의 양단에 설치되며, 시험용 루프에 흐르는 액체금속(PbLi) 및 루프관의 온도를 측정하기 위한 열전대가 설치된다. 루프 설치대를 기울였을 때 루프의 최상부에 액체금속 저장고 및 레벨센서를 설치하여 루프 내에 액체금속이 가득 채워졌는지를 레벨센서로 확인하며 루프 내에 잔존하는 기체가 저장고를 통하여 외부로 배출되게 하였다. 액체형 증식재 성능 시험용 루프 설치 후 실험은 고체 상태의 PbLi를 액체 저장용 탱크에 장착한 후 탱크의 열선의 온도 제어에 의한 PbLi의 용융점 확인, 시험용 루프에서의 전자펌프 성능 평가 등의 시험의 기본적인 실험을 수행한 후 자기장 환경에서 MHD 평가, 증식재의 순도 유지, 구조재의 부식 등의 시험을 수행할 예정이다.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.133-138
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• 2017

This paper presents a jitter characteristic improved phase locked loop (PLL) with an RC time constant circuit. In the RC time constant circuit, LPF's voltage is inputted to a comparator through small and large RC time constant circuits. The signal through a small RC time constant circuit has almost same loop filter output voltage. The signal through a large RC time constant circuit has the average value of loop filter output voltage and does as a role of reference voltage to the comparator. The output of the comparator controls the sub-charge pump which provide a current to LPF. When the loop filter output voltage increases, the sub-charge pump discharges the loop filter and decreases loop filter output voltage. When the loop filter output voltage decreases, the sub-charge pump charges the loop filter and increases loop filter output voltage. The negative feedback loop reduces the variation of loop filter output voltage resulting in jitter characteristic improvement.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.89-94
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• 2022

In this paper, a discrete-time loop filter(DLF) phase-locked loop with a Frequency Fluctuation Converting Circuit(FFCC) has been proposed. Discrete-time loop filter can improve spur characteristic by connecting the charge pump and voltage oscillator discretely unlike a conventional continuous-time loop filter. The proposed PLL is designed to operate stably by the internal negative feedback loop including the SSC acting as a negative feedback to the discrete-time loop filter of the external negative feedback loop. In addition, the phase noise is further improved by reducing the magnitude of the loop filter output voltage variation through the FFCC. Therefore, the magnitude of jitter has been reduced by 1/3 compared to the conventional structure. The proposed phase locked loop has been simulated with Hspice using the 1.8V 180nm CMOS process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.71-72
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• 2015

본 논문에서는 CPW(Coplanar waveguide) 급전되는 평면 루프 슬롯을 2.45 GHz 대역 Wi-Fi용으로 소형화 설계하는 방법에 대해 연구하였다. 제안된 구조는 직사각형 형태의 CPW 급전 루프 슬롯 안테나를 기본형으로 하여 내부 패치에 슬롯을 좌우 대칭으로 여러 개 수직 방향으로 배치한 안테나이며, FR4 기판의 한 면에 인쇄된다. 여러 가지 파라미터 값들이 안테나의 특성에 미치는 영향을 관찰하고 기존 루프 슬롯 안테나를 소형화하는 방법에 대해 연구하였다. FR4 기판에 $80mm{\times}50mm$ 크기로 2.45 GHz 대역용으로 설계된 안테나의 특성을 시뮬레이션을 통해 분석하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.335-342
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• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.