Browse > Article
http://dx.doi.org/10.6109/jkiice.2013.17.10.2409

121.15MHz Frequency Synthesizers using Multi-phase DLL-based Phase Selector and Fractional-N PLL  

Lee, Seung-Yong (Department of Electronic Engineering, Kumoh National Institute of Technology)
Lee, Pil-Ho (Department of Electronic Engineering, Kumoh National Institute of Technology)
Jang, Young-Chan (Department of Electronic Engineering, Kumoh National Institute of Technology)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.17, no.10, 2013 , pp. 2409-2418 More about this Journal
Abstract
Two frequency synthesizers are proposed to generate a clock for a sub-sampler of an on-chip oscilloscope in this paper. These proposed frequency synthesizers are designed by using a multi-phase delayed-locked loop (DLL)-based phase selector and a fractional-N phase-locked loop (PLL), and they are analyzed by comparing simulation results of each frequency synthesizer. Two proposed frequency synthesizers are designed using a 65-nm CMOS process with a 1V supply and output the clock with the frequency of 121.15 MHz when the frequency of an input clock is 125 MHz. The designed frequency synthesizer using a multi-phase DLL-based phase selector has the area of 0.167 $mm^2$ and the peak-to-peak jitter performance of 2.88 ps when it consumes the power of 4.75 mW. The designed frequency synthesizer using a fractional-N PLL has the area of 0.662 $mm^2$ and the peak-to-peak jitter performance of 7.2 ps when it consumes the power of 1.16 mW.
Keywords
frequency synthesizer; multi-phase delay-locked loop; phase selectgor; fractional-N phase-locked loop;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Zheng, Yu, "On-chip oscilloscopes for noninvasive timedomain measurement of waveforms in digital integrated circuits," IEEE Trans. VLSI Systems, pp. 336-344, June 2003.
2 Gholami M., Gholamidoon M., Hashemi M., "New method to synthesize the frequency bands with DLL-based frequency synthesizer," Communication and Signal Processing (ICCSP), 2011 International Conference on, pp. 300-304, Feb. 2011.
3 Min Wang, Zhiping Wen, Lei Chen, Yanlong Zhang, "A novel DLL-based configurable frequency synthesizer," Neural Networks and Signal Processing, 2008 International Conference on, pp. 303-306, June 2008.
4 Farhad Zarkeshvari, Peter Noel, Tad Kwasniewski, "PLL-Based Fractional-N Frequency Synthesizers," Systemon- Chip for Real-Time Applications, 2005 Proceedings. Fifth International Workshop on, pp.85-91, July 2005.
5 C.-L. Ti, Y.-H. Liu, and T.-H. Lin, "A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit," in Proc. IEEE Int. Symp. Circuits Syst., pp. 1728- 1731, May 2008.
6 T. Lin, C. Ti, and Y. Liu, "Dynamic current-matching charge pump and gated-offset linearization technique for delta-sigma fractional-N PLLs," IEEE Trans. Circuits syst. I, vol. 56, no. 5, pp. 877-885, May 2009.   DOI   ScienceOn
7 Y.-S. Kim, et. al., "A 40-to-800 MHz locking multi-phase DLL," IEEE Int. Solid-State Circuits Conf. 2007 Dig. Tech Papers, pp.306-307, Feb. 2007.
8 C.-L. Ti, Y.-H. Liu, and T.-H. Lin, "A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit," in Proc. IEEE Int. Symp. Circuits Syst., pp. 1728-1731, May 2008.
9 R. Gu and S. Ramaswamy, "Fractional-N Phase Locked Loop Design and Applications," in Proc. The 7th International Conference on ASIC, Guilin, China, pp. 327-332, Oct. 2007.