• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• The Transactions of the Korea Information Processing Society
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• v.2 no.6
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• pp.974-984
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• 1995

This paper presents a design of a high performance MULVEC (MULtithreaded architecture for the VEctor Computations), as a building block of massively parallel Processing systems. The MULVEC comes from the synthesis of the dataflow model and the extant super sclar RISC microprocesso r. The MULVEC reduces, using status fields, the number of synchronizations in the case of repeated vector computations within the same thread segment, and also reduces the amount of the context switching, network traffic, etc. After be nchmark programs are simulated on the SPARC station 20(super scalar RISC microprocessor)the performance (execution time of programs and the utilization of processors) of MULVEC and the performance(execution time of a program) of *Taccording the different numbers of node are analyzed. We observed that the execution time of the program in MULVEC is faster than that in * T about 1-2 times according the number of nodes and the number of the repetitions of the loop.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.87-94
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• 2003

In this paper, we propose an IFFT/FFT design method to minimize quantization error in IEEE 802.11a WLAN. In the proposed algorithm, the twiddle coefficient of IFFT/FFT processor is manipulated by the statistics distribution of the input data at each stage. We applies this algorithm to radix-2/$^2$ SDF architecture. Both IFFT and FFT processor shares the circuit blocks cause to the symmetric architecture. The maximum quantization error with the 10 bits length of the input and output data is 0.0021 in IFFT and FFT that has a self-loop structure with the proposed method. As a result, the proposed architecture saves 3bits for the data to keep the same resolution compared with the conventional method.

• Journal of the Korea institute for structural maintenance and inspection
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• v.12 no.2
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• pp.156-162
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• 2008

The fatigue durability test using the actual size beam was performed with a cramp joint in order to apply to the highway bridge deck slab. Three types of beam were investigated for durability performance by considering stress conditions in real bridge deck slabs, 1) A beam with major shear force applied at the joint (RC Type) 2) A beam with major bending moments applied at the joint (PSC Type) 3) A beam with the pure shear applied at the joint. The experiment for beams with cramp joints showed that the cramp joint had enough durability for fatigue regardless of the overlaid length of the looped distribution bars under the current design strength level. Moreover, it was clarified that the enough durability for fatigue under the load repetition was achieved by increasing the joint span grater than 1.5D with the consideration of the deformation due to reduction in joint stiffness.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.1-13
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• 1999

As the complexity of DSP (Digital Signal Processing) applications increases, the need for new architectures supporting efficient high-level language compilers also grows. By combining several DSP processor specific features, such as single cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping, with a RISC core having many general purpose registers and orthogonal instructions, a high-performance and compiler-friendly RISC-based DSP processors can be designed. In this study, we develop a code-converter that can exploit these DSP architectural features by post-processing compiler-generated assembly code, and evaluate the performance effects of each feature using seven DSP-kernel benchmarks and a QCELP vocoder program. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.359-369
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• 2020

In this paper, we proposed a charge pump (CP) circuit that has a wide operating range while reducing the current mismatch for the PLL that generates the main clock of the CMOS X-Ray detector. The operating range and current mismatch of the CP circuit are determined by the characteristics of the current source circuit for the CP circuit. The proposed CP circuit is implemented with a wide operating current mirror bias circuit to secure a wide operating range and a cascode structure with a large output resistance to reduce current mismatch. The proposed wide operating range cascode CP circuit was fabricated as a chip using a 350nm CMOS process, and current matching characteristics were measured using a source measurement unit. At this time, the power supply voltage was 3.3 V and the CP circuit current ICP = 100 ㎂. The operating range of the proposed CP circuit is △VO_Swing=2.7V, and the maximum current mismatch is 5.15 % and the maximum current deviation is 2.64 %. The proposed CP circuit has low current mismatch characteristics and can cope with a wide frequency range, so it can be applied to systems requiring various clock speed.

• Journal of Korean Tunnelling and Underground Space Association
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• v.9 no.2
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• pp.171-182
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• 2007

For minimizing the effect on the focus of civil traffic and environment conditions related to the excavation at the traffic jamming points, an underground station tunnel was planned with 35.5 m in length and bigger area than $200\;m^2$ in sedimentary rock mass. It faced the case that the overburden was just under 13 m. Not based on a pattern design but on the case histories of similar projects and arching effect, the design of large section tunnel under shallow overburden was investigated on three design subjects which are shape effect on the section area, application method of support pressure, and supporting and tunnel safety. According to the mechanical effect from section shape, a basic design and a preliminary design was obtained, and then supporting method of large section was planned by the supporting of NATM and a pipe roof method for subsidence prevention and mechanical stability. From the comparative study between both designs, it was found that the basic design was suitable and acceptable for the steel alignment of tunnel lining, safety and the design parameter restricted by the limit considered as partition of the excavation facilities. Through the analysis result of preliminary design showing the mechanical stability without stress concentration in tunnel arch level, it also was induced that shape effect of the large section area and yielding load obtained from deformation zone in the surrounding rock mass of tunnel have to be considered as major topics for the further development of design technique on the large section tunnel.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.3
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• pp.236-244
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• 2010

In this paper, a planar structure negative group delay circuit(NGDC) is proposed to overcome the limited availability of the component values required for the prototype lumped element(LE) NGDC design. From the prototype LE circuit analysis, general design equations and the conditions to obtain the NGD are derived and illustrated. Then the LE circuit is converted into the planar structure by applying the transmission line resonator(TLR) theory. As a design example, the LE NGDC and the proposed planar structure NGDC are designed and compared. To estimate the commercial applicability, 2-stage reflection type planar NGDC with -5.6 ns of total group delay, -0.2 dB of insertion loss, and 30 MHz of bandwidth together with 0.1 dB and 0.5 ns of the magnitude and group delay flatness, respectively, for Wideband Code Division Multiple Access(WCDMA) downlink band is fabricated and demonstrated. Also, to show the applicability of the proposed NGDC, we have configured a simple signal cancellation loop and obtained good loop suppression performance.

• Journal of Korean Society of Transportation
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• v.17 no.2
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• pp.127-135
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• 1999

Most existing progression bandwidth models maximize the single or multi weighted sum of bandwidths in the both directions to improve traffic mobility on an arterial, but they cannot be applied to general networks. Even though a few models formulating a looped network problem cannot be applied to networks have not loops. Also they have some defects in optimizing phase sequences. Therefore, the objective of this study is to develope a mathematical formulation of the synchronization problem for a general traffic network. The goal is achieved successfully by introducing the signal phasing for each movement and expanding the mixed integer linear programming of MAXBAND. The experiments indicate that the proposed model can formulate the general traffic network problem mere efficiently than any other model. In conclusion, this model may optimize signal time to smooth progression in the general networks.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.15 no.2
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• pp.263-268
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• 1997

Software structure must be dynamic to support new geospatial information sources and their object-oriented implementation on the Web. JAVA is interactive, platform idependent and object-oriented language and meets all needs on Internet GSIS. This paper introduce JAVA based GIS program to manipulates various geographic data on Internet, communicating interactively and transfer real-time data between server and client. This and this program analysis roof detector in all part of Pusan area and indicates the traffic states, road surface conditions, weather information, shortest cut, and road names in JAVA client windows. Also this study shows various techniques in expression real time traffic informations.