• Journal of the Korean Crystal Growth and Crystal Technology
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• v.13 no.6
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• pp.272-278
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• 2003

$Bi_4Ti_3O_{12}$ (BIT) and $(Bi_{3.25}La_{0.75})(Ti_{2.97}V_{0.03})O_{12}$ (BLTV) thin films were deposited on ITO/glass substrates by metal organic chemical vapor deposition (MOCVD) using ultrasonic spraying. After deposition of the films in oxygen atmosphere for 30 min, the films were heated by rapid thermal annealing (RTA) method, especially direct insertion, at various temperatures. The films were investigated on phase formation temperature, microstructure and electrical properties. From x-ray diffraction (XRD) patterns, the perovskite phase formation temperature of BLTV thin film was about $600^{\circ}C$ which was lower than that of BIT, $650^{\circ}C$. The leakage current of the BLTV thin film was measured to be $1.52\times 10^{-9}$A/$cm^2$ at an applied voltage of 1 V. The remanent polarization (Pr) and coercive field (Ec) values of the BLTV film deposited at $650^{\circ}C$ were $5.6\muC/cm^2$ and 96.5 kV/cm, respectively.

• Journal of IKEEE
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• v.25 no.2
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• pp.302-308
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• 2021

A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-nm CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-V_pp differential sinusoidal analog input with frequency of 1 MHz. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.129-134
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• 2014

This paper presents a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) which consists of a digital-to-analog converter (DAC), a SAR logic, and a comparator. The designed asynchronous SAR ADC with a rail-to-rail input range uses a binary weighted DAC using metal-oxide-metal (MOM) capacitor to improve sampling rate. The proposed 10-bit 10-MS/s asynchronous SAR ADC is fabricated using a 0.18-${\mu}m$ CMOS process and its active area is $0.103mm^2$. The power consumption is 0.37 mW when the voltage of supply is 1.1 V. The measured SNDR are 54.19 dB and 51.59 dB at the analog input frequency of 101.12 kHz and 5.12 MHz, respectively.

• The Korean Journal of Ceramics
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• v.4 no.2
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• pp.83-89
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• 1998

The structure refinements and the electrical and magnetoelectric measurements were performed for BIT.1BF and BIT.2BT. The tetragonal distortion of the ab plane became lessened with the addition of $4BiFeO_3 into Bi_4Ti_3O_{12}$ significantly. However, the tilting of the outer-oxygen octahedra of the perovskite unit and the elongatin of the $(Bi_2O_2)^{2+}$ layers became more pronounced. For the both phases, the bariations of dielectric properties and electrical conductivities at high temperatures showed that the ferroelectic I-rerroelectric II phase transition existed before reaching the Curie temperature. The electrical conductivity became higher with the increase of $Fe^{3+}$ ions, implying that the electron transfer increased correspondingly. The magnetoelectric effect was observed linear up to ~8 kOe, which was stronger in BIT.1BF than BIT.2BF. This behavior indicates that the distortion of the ab plane may affect the induced polarization as well as magnetic moment.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.98-107
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• 1993

This paper describes a design of a multi-bit oversampling noise-shaping D/A converter which achieves a resolution of 12 bits using oversampling technique. In the architecture the essential block which determines the whole accuracy is the analog internal D/A converter, and the designed charge-integration internal D/A converter adopts a differential structure in order to minimize the reduction of the resolution due to process variation. As the proposed circuit is driven by signal clocks which contains the information of the data variation from the noise-shaping coder, it minimizes the disadvantage of a charge-integration circuit in the time axis. In order to verify the circuit, it was integrated with the active area of 950$\times$650${\mu}m^{2}$ in a double metal 1.5-$\mu$m CMOS process, and testified that it can achieve a S/N ratio of 75 dB and a S/(N+D) ratio of 60 dB for the signal bandwidth of 9.6 kHz by the measurement with a spectrum analyzer.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.293-294
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• 2014

본 논문에서는 MOS 커패시터를 이용하여 12비트 1MSps 연속 근사화 레지스터 아날로그-디지털 변환기(Successive Approximation Register Analog-to-Digital Converter, SAR ADC)를 설계하였다. 설계된 아날로그-디지털 변환기는 매그나칩/SK하이닉스 $0.18{\mu}m$ 공정을 이용하였으며, Cadence Tool을 이용하여 시뮬레이션 및 레이아웃을 하였다. 시뮬레이션 결과 1.8V의 공급전압에서 전력 소모는 3.22mW였고, 유효 비트수는 11.5bit의 결과를 보였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.418-425
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• 2012

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit pre-computation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weight-column code during the write operation and is designed by replacing 0's with 1's at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the odd-weight- column code, the implementation based on the proposed SEC-DED code with check bit pre-computation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.12
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• pp.3037-3054
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• 2013

Interference between primary user (PU) and secondary user (SU) transceivers should be mitigated in order to implement underlay spectrum sharing in cognitive radio networks (CRN). Considering this scenario, an improved joint subcarrier and bit allocation scheme for cognitive user with primary users' cooperation (PU Coop) in CRN is proposed. In this scheme, the optimization problem is formulated to minimize the average interference power level at the PU receiver via PU Coop, which guarantees a higher primary signal to interference plus noise ratio (SINR) while maintaining the secondary user total rate constraint. The joint optimal scheme is separated into subcarrier allocation and bit assignment in each subcarrier via arith-metric geo-metric (AM-GM) inequality with asymptotical optimization solution. Moreover, the joint subcarrier and bit optimization scheme, which is evaluated by the available SU subcarriers and the allocated bits, is analyzed in the proposed PU Coop model. The performance of cognitive spectral efficiency and the average interference power level are investigated. Numerical analysis indicates that the SU's spectral efficiency increases significantly compared with the PU non-cooperation scenario. Moreover, the interference power level decreases dramatically for the proposed scheme compared with the traditional Hughes-Hartogs bit allocation scheme.

• Journal of IKEEE
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• v.21 no.3
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• pp.260-263
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• 2017

Based on several CPU cores, an SoC including ADCs, DC-DC converter and 2M-byte SRAM is proposed in this paper. The CPU core consists of a 12-bit MENSA, a 32-bit Symmetric multi-core processor, as well as 16-bit CDSP. To eliminate the external SDRAM memory, internal 2M-byte SRAM is implemented. Because the SRAM normally occupies huge area, the parasitic components reduce the speed of SoC. In this work, the SRAM blocks are divided into small pieces to reduce the parasitic components. The proposed SoC is developed in a standard 55nm CMOS process and the speed of SoC is 200MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.13-20
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• 2008

In this paper, an 1.8V 12-bit 10MSPS CMOS A/D converter (ADC) is described. The architecture of the proposed ADC is based on a folding and interpolation using an even folding technique. For the purpose of improving SNR, cascaded-folding cascaded-interpolation technique, distributed track and hold are adapted. Further, a digital encoder algorithm is proposed for efficient digital process. The chip has been fabricated with $0.18{\mu}m$ 1-poly 4-metal n-well CMOS technology. The effective chip area is $2000{\mu}m{\times}1100{\mu}m$ and it consumes about 250mW at 1.8V power supply. The measured SNDR is about 46dB at 10MHz sampling frequency.