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http://dx.doi.org/10.5573/JSTS.2012.12.4.418

Efficient Implementation of Single Error Correction and Double Error Detection Code with Check Bit Pre-computation for Memories  

Cha, Sanguhn (Sch. EE., Yonesi University)
Yoon, Hongil (Sch. EE., Yonesi University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.12, no.4, 2012 , pp. 418-425 More about this Journal
Abstract
In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit pre-computation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weight-column code during the write operation and is designed by replacing 0's with 1's at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the odd-weight- column code, the implementation based on the proposed SEC-DED code with check bit pre-computation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.
Keywords
Error correction code; single error correction and double error detection code; check bit pre-computation; extended Hamming code and memory;
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Times Cited By KSCI : 1  (Citation Analysis)
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1 B. Polianskikh and Z. Zilic, "Design and implementation of error detection and correction circuitry for multilevel memory protection," Multiple-Valued Logic, 2002. ISMVL 2002. Proceedings 32nd IEEE International Symposium on, pp. 89-95, 2002.
2 W. Gao and S. Simmons, "A study on the VLSI implementation of ECC for embedded DRAM," Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on, vol. 1, pp. 203-206, 2003.
3 M. Nicolaidis, T. Bonnoit, and N.-E. Zergainoh, "Eliminating speed penalty in ECC protected memories," Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1-6, 2011.
4 Z. Al-Ars and A. J. van de Goor, "Soft faults and importance of stresses in memory testing," Design, Automation and Test in Europe Conference and Exhibition, pp. 1084-1089, Feb. 2004.
5 R. C. Baumann, "Radiation-induced soft errors in advanced semiconductor technologies," Device and Materials Reliability, IEEE Transactions on, vol. 5, pp. 305-316, 2005.   DOI   ScienceOn
6 P. E. Dodd, M. R. Shaneyfelt, J. R. Schwank, and J. A. Felix, "Current and future challenges in radiation effects on CMOS electronics," Nuclear Science, IEEE Transactions on, vol. 57, pp. 1747-1763, 2010.   DOI   ScienceOn
7 R. W. Hamming, "Error detecting and error correcting code," Bell System Technical Journal, vol. 26, pp. 147-160, Apr.1950.
8 M. Y. Hsiao, "A class of optimal minimum oddweight- column SEC-DED codes," Research and Development, IBM Journal of, vol. 14, Issue 4, pp. 395-401, Jul. 1970.   DOI
9 Eiji Fujiwara, "Code design for dependable systems - Theory and practical applications," Wiley-interscience, 2006.
10 S. Cha, Y. Lee, and H. Yoon, "A low-power ECC check bit generator implementation in DRAMs," Journal of Semiconductor Technology and Science, vol. 6, no. 4, pp. 252-256, Dec. 2006.   과학기술학회마을
11 P. K. Lala, P. Thenappan, and M. T. Anwar, "Single error correcting and double error detecting coding scheme," IET Electronics Letters, vol. 41, Issue 13, pp. 758-760, Feb. 2005.   DOI   ScienceOn
12 S. Cha and H. Yoon, "High speed, minimal area, and low power SEC code for DRAMs with large I/O data widths," Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, pp. 3026-3029, May 2007.