• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.129-134
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• 2014

This paper presents a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) which consists of a digital-to-analog converter (DAC), a SAR logic, and a comparator. The designed asynchronous SAR ADC with a rail-to-rail input range uses a binary weighted DAC using metal-oxide-metal (MOM) capacitor to improve sampling rate. The proposed 10-bit 10-MS/s asynchronous SAR ADC is fabricated using a 0.18-${\mu}m$ CMOS process and its active area is $0.103mm^2$. The power consumption is 0.37 mW when the voltage of supply is 1.1 V. The measured SNDR are 54.19 dB and 51.59 dB at the analog input frequency of 101.12 kHz and 5.12 MHz, respectively.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.54-58
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• 2002

This paper describes the theoretical analysis and performance of a 2.4㎓ bulk-driven downconversion mixer, where the LO signal is input via the bulk. A mixer core designed with a 0.18$\mu\textrm{m}$ CMOS process is able to operate under 0.8V∼1V supply voltage. The RF, LO, and IF port frequencies are 2.45㎓, 2.4㎓, and 50MHz, respectively. The measurement results exhibit conversion gain of -1.8㏈, l㏈ compression point of -17㏈m and IIP3 of -4㏈m with 0㏈m LO power. The power consumption is as small as 4mW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.2 s.93
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• pp.189-193
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• 2005

In this paper, we propose a direct conversion double-balanced down-converter fer MB-OFDM W system, which is implemented using $0.18\;{\mu}m$ CMOS technology and its measurement results are shown. The proposed down-converter adopts a resistive current-source instead of general transconductance stage using MOS transistor to achieve wideband characteristics over RF input frequency band $3\~5\;GHz$ with good gain flatness. The measured conversion gain is more than +3 dB, and gain flatness is less than 3 dB for three UWB channels. The dc consumption of this work is only 0.89 mA from 1.8 V power supply, leading to the low-power W application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.35-40
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• 2005

A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter-the key building blocks of digital PLL (DPLL), there is no need for the 03de-off between jitter, power consumption and silicon area. The DCPLL was implemented in a $0.18\mu$m CMOS process and the active area is 1mm $\times$0.35 mm The DCPLL consumes S9mW during the normal opuation and $984\{mu}W$ during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps ms jitter.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.91-98
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• 2013

Magnetic sensor chip for measuring bio-magnetism is implemented in $0.18{\mu}m$ CMOS technology. The magnetic sensor chip consists of a small-sized high inductance coil sensor and an instrumentation amplifier (IA). High inductance coil sensor with suitable sensitivity and bandwidth for measurement of bio-magnetic signal is designed using electromagnetic field simulation. Low gm operational transconductance amplifier (OTA) using transconductance reduction techniques is designed for on-chip solution. Output signal sensitivity of magnetic sensor chip is $3.25fT/{\mu}V$ and reference noise of 21.1fT/${\surd}$Hz. Proposed IA is designed along with band pass filters(BPF) to reduce magnetic signal noise by using current feedback techniques. Proposed IA achieves a common mode rejection ratio of 117.5dB while the input noise referred is kept below $0.87{\mu}V$.

• Journal of IKEEE
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• v.14 no.1
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• pp.33-39
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• 2010

In this paper, a 5Gb/s receiver with an adaptive equalizer for serial link interfaces is proposed. For effective gain control, a least-mean-square (LMS) algorithm was implemented with two internal signals of slicers instead of output node of an equalizing filter. The scheme does not affect on a bandwidth of the equalizing filter. It also can be implemented without passive filter and it saves chip area and power consumption since two internal signals of slicers have a similar DC magnitude. The proposed adaptive equalizer can compensate up to 25dB and operate in various environments, which are 15m shield-twisted pair (STP) cable for DisplayPort and FR-4 traces for backplane. This work is implemented in $0.18-{\mu}m$ 1-poly 4-metal CMOS technology and occupies $200{\times}300{\mu}m^2$. Measurement results show only 6mW small power consumption and 2Gbps operating range with fabricated chip. The equalizer is expected to satisfy up to 5Gbps operating range if stable varactor(RF) is supported by foundry process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.3
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• pp.685-690
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• 2013

This paper has proposed a multi-channel and wide gain-range baseband circuit blocks for the IEEE 802.15.4g MR-OFDM SUN systems. The proposed baseband circuit blocks consist of two negative-feedback VGAs, an active-RC 5th-order chebyshev low-pass-filter, and a DC-offset cancellation circuit. The proposed baseband circuit blocks provide 1 dB cut-off frequencies of 100 kHz, 200 kHz, 400 kHz, and 600 kHz respectively, and achieve a wide gain-range of +7 dB~+84 dB with 1 dB step. In addition, a DC-offset cancellation circuit has been adopted to mitigate DC-offset problems in direct-conversion receiver. Simulation results show a maximum input differential voltage of $1.5V_{pp}$ and noise figure of 42 dB and 37.6 dB at 5 kHz and 500 kHz, respectively. The proposed I-and Q-path baseband circuits have been implemented in $0.18-{\mu}m$ CMOS technology and consume 17 mW from a 1.8 V supply voltage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.346-349
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• 2013

This paper describes a triple-input energy harvesting circuit using solar, vibration and thermoelectric energy with MPPT(Maximum Power Point Tracking) control. The designed circuit employs MPPT control to harvest maximum power available from a solar cell, PZT vibration element and thermoelectric generator. The harvested energies are simultaneously combined and stored in a storage capacitor, and then managed and transferred into a sensor node by PMU(Power Management Unit). MPPT controls are implemented using the linear relation between the open-circuit voltage of an energy transducer and its MPP(Maximum Power Point) voltage. The proposed circuit is designed in a CMOS 0.18um technology and its functionality has been verified through extensive simulations. The designed chip occupies $945{\mu}m{\times}995{\mu}m$.

• Transactions on Electrical and Electronic Materials
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• v.18 no.4
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• pp.185-189
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• 2017

This paper proposes a low power frequency divider for an integrated CMOS phase-locked loop (PLL). An injection-locked frequency divider (ILFD) was designed, along with a current-mode logic (CML) frequency divider in order to obtain a broadband and high-frequency operation. A ring oscillator was designed to operate at 1.2 GHz, and the ILFD was used to divide the frequency of its input signal by two. The structure of the ILFD is similar to that of the ring oscillator in order to ensure the frequency alignment between the oscillator and the ILFD. The CML frequency divider was used as the second stage of the divider. The proposed frequency divider was applied in a conventional PLL design, using a 0.18 ${\mu}m$ CMOS process. Simulation shows that the proposed divide-by-two ILFD and the divide-by-eight CML frequency dividers operated as expected for an input frequency of 1.2 GHz, with a power consumption of 30 mW.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.187-188
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• 2007

This paper describes a simple and high-performance LDO regulator designed using a $0.18{\mu}m$ CMOS process. It is designed to provide a regulated voltage for on-chip small loads instead of for off-chip heavy loads. Since the load capacitance is very small in this applications, the frequency compensation can be easily achieved without a buffer. The designed LDO drives a load current up to 15mA and dissipates only 12uA quiescent current. The line regulation is and the load regulation is for a 9mA load step. The PSRR at 10kHz is 54dB.