• 대한전자공학회논문지SD
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• 제42권8호
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• pp.53-60
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• 2005

최근 낮은 기가비트급 광통신 집적회로의 구현에 sub-micron CMOS 공정이 적용되고 있다. 본 논문에서는 표준 0.35mm CMOS 공정을 이용하여 4채널 3.125Gb/s 차동 전치증폭기 어레이를 구현하였다. 설계한 각 채널의 전치증폭기는 차동구조로 regulated cascode (RGC) 설계 기법을 이용하였고, 액티브 인덕터를 이용한 인덕티브 피킹 기술을 이용하여 대역폭 확장을 하였다 Post-layout 시뮬레이션 결과, 각 채널 당 59.3dBW의 트랜스임피던스 이득, 0.5pF 기생 포토다이오드 캐패시턴스에 대해 2.450Hz의 -3dB 대역폭, 그리고 18.4pA/sqrt(Hz)의 평균 노이즈 전류 스펙트럼 밀도를 보였다. 전치증폭기 어레이의 공급전원은 단일전압 3.3V 이고, 전력소모는 92mw이다. 이는 4채널 RGC 전치증폭기 어레이가 저전력, 초고속 광인터컨넥트 분야에 적합함을 보여준다.

• Journal of information and communication convergence engineering
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• 제10권2호
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• IEIE Transactions on Smart Processing and Computing
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• 제5권2호
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• pp.71-76
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• 2016

A controller area network (CAN) receiver measures differential voltage on a bus to determine the bus level. Since 3.3V transceivers generate the same differential voltage as 5V transceivers (usually ${\geq}1.5V$), all transceivers on the bus (regardless of supply voltage) can decipher the message. In fact, the other transceivers cannot even determine or show that there is anything different about the differential voltage levels. A new CMOS RC oscillator insensitive supply voltage for clock generation in a CAN transceiver was fabricated and tested to compensate for this drawback in CAN communication. The system consists of a symmetrical circuit for voltage and current switches, two capacitors, two comparators, and an RS flip-flop. The operational principle is similar to a bistable multivibrator but the oscillation frequency can also be controlled via a bias current and reference voltage. The chip test experimental results show that oscillation frequency and power dissipation are 500 kHz and 5.48 mW, respectively at a supply voltage of 3.3 V. The chip, chip area is $0.021mm^2$, is fabricated with $0.18{\mu}m$ CMOS technology from SK hynix.

• ETRI Journal
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• 제29권4호
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• 대한전자공학회논문지SD
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• 제39권6호
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• pp.69-77
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• 2002

본 논문에서는 캐쉬를 지원하는 ARM940T, TeakLite DSP 코어 그리고 다른 주변 블록이 내장된 0.18㎛ CMOS 공정기술을 적용한 CDMA2000 lx를 지원하는 이동국 모뎀 칩 구현에 대하여 기술한다. 또한 구현 칩을 효율적으로 검증할 수 있는 고유한 검증 방법론과 구현된 칩이 에뮬레이션용 프로세서로 활용될 수 있는 방법을 보인다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 춘계학술대회
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• pp.693-695
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• 2016

무작위와 체계적인 것에 의한 지터를 제어하는 지연고정 루프가 소개 되었다. AC는 연속적인 지연단의 지연 시간을 평균화 하고 모든 지연 단의 지연시간을 동일하게 한다. 지연위상고정을 기반으로한 0.18um CMOS공정으로 제작된 클럭 발생기의 측정결과는 13.4ps rms 지터 크기를 보였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.627-628
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• 2006

A low-voltage switched-capacitor $2^{nd}$-order $\Sigma\Delta$ modulator using full feed-forward is introduced. It has two advantages: the unity signal transfer function and reduced signal swings inside the $\Sigma\Delta$ loop. These features greatly relax the DC gain and output swing requirements for Op-Amp in the low-voltage $\Sigma\Delta$ modulator. Implemented by a 0.18-${\mu}m$ CMOS technology, the $\Sigma\Delta$ modulator satisfies performance requirements for WCDMA and CDMA2000 standards.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.842-846
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• 2016

This paper presents a DC-DC buck converter which uses a sleep control to improve the power efficiency in a few mW light load condition. The sleep control turns off analog controller building blocks to reduce the static power losses during the off-duty period of pulse width modulation. For verification, a buck converter has been implemented in a $0.18{\mu}m$ CMOS process. The power efficiency has been improved from 76.7% to 82.5% with a 1.2 mW load. The maximum power efficiency is 95% with a 9 mW load.

• 전기학회논문지
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• 제60권2호
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• pp.320-324
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• 2011

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 GHz charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate $0.5{\mu}A$ current mismatch in CP. It was designed in a standard $0.13{\mu}m$ CMOS technology. The maximum calibration time is $33.6{\mu}s$ and the average power is 18.38mW with 1.5V power supply and effective area is $0.1804mm^2$.

• 한국통신학회논문지
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• 제39C권1호
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• pp.82-89
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• 2014

최근 M2M/IoT에 대한 관심이 높아지면서 디바이스의 위치와 자세 등을 인식할 수 있는 동작 인식 센서의 필요성이 대두되고 있다. 본 논문에서는 소형의 디바이스에 적합하도록 저잡음, 저전력, 초소형 6축 관성센서 IC를 구현하였다. 본 논문에서 구현된 IC는 3축의 압전형 자이로 센서와 3축의 압저항형 가속도 센서를 사용하며, 3축의 자이로스코프 감지 회로, 자이로스코프 센서 구동 회로, 3축의 가속도 감지 회로, 16bit sigma-delta ADC, 디지털 필터와 제어 회로로 구성되어 있다. 본 IC은 TSMC $0.18{\mu}m$ mixed signal CMOS공정으로 개발되었으며, STM사의 6축 관성 센서인 LSM330의 소비전류 6.1mA보다는 약 27% 낮은 4.5mA의 소비 전류로 동작한다.