• 한국정보통신학회논문지
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• 제20권7호
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• pp.1303-1310
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• 2016

본 논문에서는 전원전압 0.5V의 심전도 검사기(ECG)를 설계하고 칩으로 제작하여 성능을 확인하였다. ECG는 계측 증폭기, 6차 gm-C 저역 통과 필터 그리고 가변이득증폭기로 구성되어 있다. 계측증폭기는 이득이 34.8dB, 6차 gm-C 저역 통과 필터는 400Hz의 차단주파수를 가지게 설계되었다. 저역 통과 필터의 연산 트랜스컨덕턴스 증폭기는 저전압 동작을 위하여 차동 바디 입력 방법을 사용하였다. 가변이득증폭기의 이득 범위는 6.1~26.4dB로 설계되었다. 설계된 심전도 검사기는 TSMC $0.18{\mu}m$ CMOS 공정을 이용하여 $858{\mu}m{\times}580{\mu}m$의 칩크기로 제작되었다. 측정은 입력 신호를 포화시키지 않도록 외부 연결 저항을 조절하여 이득을 낮춘 상태에서 진행한바, 중간 주파수 이득 28.7dB, 대역폭은 0.5 - 630Hz을 얻었으며, 전원전압 0.5V에서 동작함을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.168-173
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• 2004

A low power CMOS receiver baseband analog circuit based on alternating filter and gain stage is reported. For the given specifications of the baseband analog block, optimum allocation of the gain, IIP3 and NF of the each block was performed to minimize current consumption. The fully integrated receiver BBA chain is fabricated in $0.18\;{\mu}m$ CMOS technology and IIP3 of 30 dBm with a gain of 55 dB and noise figure of 31 dB are obtained at 4.86 mW power consumption.

• Journal of electromagnetic engineering and science
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• 제8권3호
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• pp.114-118
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• 2008

Direct-conversion RF front-end for 5-GHz WLAN is implemented in $0.18-{\mu}m$ CMOS technology. The front-end consists of a low noise amplifier, and low flicker noise down-conversion mixers. For the mixer, an inductor is included to resonate out parasitic tail capacitances in the transconductance stage at the operating frequency, thereby improves the flicker noise performance of the mixer, and the overall noise performance of the front-end. The receiver RF front-end has 6.5 dB noise figure, - 13 dBm input IP3, and voltage conversion gain of 20 dB with the power consumption of 30 mW.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.417-418
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• 2008

A quadrature voltage controlled oscillator(QVCO) with MOS-varactors has been fabricated for X-band applications. The QVCO consists of two cross -coupled differential cores and buffer amplifiers, which has fabricated in TSMC $0.18{\mu}m$ CMOS process. The QVCO exhibits a frequency tuning range from 8.38 GHz to 10.62 GHz. The phase noise is -88 dBc/Hz at 1 MHz-offset frequency. The total bias current is 25 mA including four buffer amplifiers.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.459-460
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• 2008

In this paper, a 10Gbps clock and data recovery circuit is designed in $0.18{\mu}m$ CMOS technology. The circuit incorporates a multiphase LC oscillator, a quarter-rate Bang-Bang phase detector, a charge pump and a second order loop filter. The simulation results show that the designed circuit has a peak-to-peak clock jitter of 4.2ps and a peak-to-peak recovered data jitter of 8ps while consuming about 80mW from a 1.8V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권3호
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• pp.153-159
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• 2009

A CMOS frequency synthesizer for $5{\sim}6$ GHz UNII-band sub-harmonic direct-conversion receiver has been developed. For quadrature down-conversion with sub-harmonic mixing, octa-phase local oscillator (LO) signals are generated by an integer-N type phase-locked loop (PLL) frequency synthesizer. The complex timing issue of feedback divider of the PLL with large division ratio is solved by using multimodulus prescaler. Phase noise of the local oscillator signal is improved by employing the ring-type LC-tank oscillator and switching its tail current source. Implemented in a $0.18{\mu}m$ CMOS technology, the phase noise of the LO signal is lower than -80 dBc/Hz and -113 dBc/Hz at 100 kHz and 1MHz offset, respect-tively. The measured reference spur is lower than -70 dBc and the power consumption is 40 m W from a 1.8 V supply voltage.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.617-618
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• 2006

A CMOS quadrature Up-converter for a direct-conversion receiver of 5.15-5.825GHz wireless LAN is described. The Up-converter consists of two sub-harmonic mixers, for I and Q channels, and an LO generation network. In order to decrease the number of inductor, I and Q path are merged. The simulation results including all the parasitics show -17.3dB conversion gain at center and -8 dBv oIP3 while consuming 22.968mW under 1.8V supply. The quadrature Up-converter is under fabrication with the other transmitter blocks in a $0.18{\mu}m$ CMOS technology.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.501-503
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• 2008

This paper presents the design of a 2.4 GHz low phase noise fully integrated LC Voltage-Controlled-Oscillator (VCO) in $0.18{\mu}m$ CMOS technology. The VCO is without any tail bias current sources for a low phase noise and, in which differential varactors are adopted for the symmetry of the circuit. At the same time, the use of differential varactors pairs reduces the tuning range, i.e., the frequency range versus VTUNE, so that the phase noise becomes lower. The simulation results show the achieved phase noise of -138.5 dBc/Hz at 3 MHz offset, while the VCO core draws 3.9mA of current from a 1.8V supply. The tuning range is from 2.28GHz to 2.55 GHz.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.197-198
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• 2007

In this paper, a 10Gbps Clock and Data Recovery circuit is designed in $0.18{\mu}m$ CMOS Technology. The circuit incorporates a multiphase LC oscillator, a quarter-rate Bang-Bang phase detector, a Charge Pump and a second order loop filter. The simulation results show that the designed circuit has a peak-to-peak clock jitter of 4.1ps and a peak-to-peak recovered data jitter of 8ps while consuming about 44mW from a 1.8V supply.

• ETRI Journal
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• 제29권5호
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• pp.670-672
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• 2007

An ultra-wideband low-noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18-${\mu}m$ CMOS process and adopts a two-stage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input-impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are measured over 3.4 to 8.2 GHz while consuming 17.3 mW of power. The Proposed UWB LNA achieves a measured power-gain bandwidth product of 399.4 GHz.