• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.1-7
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• 2006

An on chip voltage down converter (VDC) using the self temperature-compensation techniques is proposed. At a different gate bias voltage, PMOSFET shows different source to drain current characteristic according to the temperature variation. The proposed VDC can reduce its temperature dependency by the source to drain current ratio of two PMOSFET with different gate bias respectively. Proposed circuit is fabricated in Dongbu-anam $0.18{\mu}m$ CMOS process and experimental results show its temperature dependency of $-0.49mV/^{\circ}C$ and external supply dependency of 6mV/V. Total current consumption is only $1.1{\mu}A@2.5V$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.22-29
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• 2007

A 2.5Gb/s 2:1 multiplexer(MUX) IC using $0.18{\mu}m$ CMOS was designed and fabricated. Inductive peaking technology was used to improve the performance. On-chip micro spiral inductor was designed to maximize the inductive peaking effect without increasing the chip area much. The designed 4.7 nH micro-spiral inductor was $20\times20{\mu}m2$ in size. 2:1 MUX with and without micro spiral inductors were compared. The rise and fall time was improved more than 23% and 3% respectively using the micro spiral inductors for 1.25Gb/s signal. For 2.5 Gb/s signal, fall and rise time was improved 5.3% and 3.5% respectively. It consumed 61mW and voltage output swing was 1$180mV_{p-p}$ at 2.5Gb/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.28-36
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• 2008

This paper describes a low-power CMOS analog front-end block for UHF band RFID tag chips. It satisfies ISO/IEC 18000-6C and includes a memory block for test. For reducing power consumption, it operates with an internally generated power supply of 1V. An ASK demodulator using a current-mode schmitt trigger is proposed and designed. The proposed demodulator can more exactly demodulate than conventional demodulator with low current consumption. It is designed using a $0.18{\mu}m$ CMOS technology. Measurement results show that it can operate properly with an input as low as $0.25V_{peak}$ and consumes $2.63{\mu}A$. The chip size is $0.12mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.33-38
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• 2017

In this paper, a 4-channel common-cathode VCSEL diode driver array with 3.125 Gb/s per channel operation speed is realized. In order to achieve faster speed of the switching main driver with relatively large transistors, the transmitter array chip consists of a pre-amplifier with active inductor stage and also an input buffer with modified equalizer, which leads to bandwidth extension and reduced current consumption. The utilized VCSEL diode provides inherently 2.2 V forward bias voltage, $50{\Omega}$ resistance, and 850 fF capacitance. In addition, the main driver based upon current steering technique is designed, so that two individual current sources can provide bias currents of 3.0 mA and modulation currents of 3.3 mA to VCSEL diodes. The proposed 4-channel VCSEL driver array has been implemented by using a $0.11-{\mu}m$ CMOS technology, and the chip core occupies the area of $0.15{\times}0.18{\mu}m^2$ and dissipates 22.3 mW per channel.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.86-93
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• 2008

A low-power, low-noise, highly-linear hybrid balun circuit is proposed for 2.4-GHz fully differential CMOS direct conversion receivers. The hybrid balun is composed of a passive transformer and loss-compensating auxiliary amplifiers. Design issues regarding the optimal signal splitting and coupling between the transformer and compensating amplifiers are discussed. Implemented in $0.18{\mu}m$ CMOS process, the 2.4 GHz hybrid balun achieves 2.8 dB higher gain and 1.9 dB lower noise figure than its passive counterpart and +23 dBm of IIP3 only at a current consumption of 0.67 mA from 1.2 V supply. It is also examined that the hybrid balun can remarkably lower the total noise figure of a 2.4 GHz fully differential RF receiver only at a cost of 0.82 mW additional power dissipation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.88-90
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• 2012

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a rail-to-rail input range. The proposed SAR ADC consists of a capacitor digital-analog converter (DAC), a SAR logic and a comparator. To reduce the frequency of an external clock, the internal clock which is asynchronously generated by the SAR logic and the comparator is used. The time-domain comparator with a offset calibration technique is used to achieve a high resolution. To reduce the power consumption and area, a split capacitor-based differential DAC is used. The designed asynchronous SAR ADC is fabricated by using a 0.18 um CMOS process, and the active area is $420{\times}140{\mu}m^2$. It consumes the power of 0.818 mW with a 1.8 V supply and the FoM is 91.8 fJ/conversion-step.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.35-41
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• 2013

An efficient multi-stage rectifier for wireless power transfer in deep implant medical devices is implemented using $0.18-{\mu}m$ CMOS technology. The presented three-stage rectifier employs a cross-coupled topology to boost a small input AC signal from the external device to produce a 1.2-1.5 V output DC signal for the implant device. The designed rectifier achieves a maximum measured power conversion efficiency of 70% at 13.56 MHz under the conditions of a low 0.6-Vpp RF input signal with a $10-k{\Omega}$ output load resistance.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.67-73
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• 2015

This paper presents a fully integrated 3 - 5 GHz IR-UWB(impulse radio ultra-wide band) RFIC for Location based system. The receiver architecture adopts the energy detection method and for high speed sampling, the equivalent time sampling technique using the integrated DLL(delay locked loop) and 4 bit ADC. The digitally synthesized UWB impulse generator with low power consumption is also designed. The designed IR-UWB RFIC is implemented on $0.18{\mu}m$ CMOS technology. The receiver's sensitivity is -85.7 dBm and the current consumption of receiver and transmitter is 32 mA and 25.5 mA respectively at 1.8 V supply.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.7
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• pp.667-674
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• 2005

In this paper the gate overlap length of the LDMOST is optimized for obtaining longer device lifetime. The LDMOSI device with drift region is fabricated using the $0.25\;{\mu}m$ CMOS Process. The gate overlap lengths on drift region are $0.1\;{\mu}m,\;0.4\;{\mu}m\;0.8\;{\mu}m\;and\;1.1\;{\mu}m$, respectively. The breakdown voltages, on-resistances and hot-carrier degradations of the fabricated LDMOST devices are characterized. The LDMOST device with gate overlap length of $0.4\;{\mu}m$ showed the longest on-resistance lifetime, 0.02 years and breakdown voltage of 22 V and on-resistance of $23\;m\Omega{\cdot}mm^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.158-165
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• 2013

In this paper, a new circuit topology of an ultra-wideband (UWB) 3.1-10.6GHz CMOS low noise amplifier is presented. The proposed UWB low noise amplifier is designed utilizing RC feedback and LC filter networks which can provide good input impedance matching. In this design, the current-reused topology is adopted to reduce the power consumption and the inductor-peaking technique is applied for the purpose of bandwidth extension. The performance results of this UWB low noise amplifier simulated in $0.18-{\mu}m$ CMOS process technology exhibit a power gain of 14-14.9dB, an input matching of better than -10.8dB, gain flatness of 0.9dB, and a noise figure of 2.7-3.3dB in the frequency range of 3.1-10.6GHz. In addition, the input IP3 is -5dBm and the power consumption is 12.5mW.