대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

UHF 대역 RFID 태그 칩을 위한 저전력 CMOS 아날로그 Front-End 회로 설계

Design of a Low-Power CMOS Analog Front-End Circuit for UHF Band RFID Tag Chips

  • Shim, Hyun-Chul (Dept. of Electronics Engineering, University of Incheon) ;
  • Cha, Chung-Hyun (Dept. of Electronics Engineering, University of Incheon) ;
  • Park, Jong-Tae (Dept. of Electronics Engineering, University of Incheon) ;
  • Yu, Chong-Gun (Dept. of Electronics Engineering, University of Incheon)
  • 발행 : 2008.06.25
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초록

본 논문에서는 UHF 대역 RFID 태그(tag) 칩을 위한 저전력 CMOS 아날로그 회로를 설계하였다. 설계된 아날로그 front-end 블록은 국제표준인 ISO/EC 18000-6C 표준규격을 따르며, 성능테스트를 위한 메모리 블록을 포함하고 있다. 모든 회로를 1V에서 동작하도록 하여 세부 회로들의 전력소모를 최소화 하였으며, 보다 적은 전류소모로 정확한 복조를 위해 전류 모드 슈미트 트리거를 이용한 ASK 복조기를 제안 하였다. 설계된 회로는 $0.18{\mu}m$ CMOS 공정을 이용하여 칩으로 제작되었으며, 측정결과 최소 $0.25V_{peak}$ 입력으로 동작 가능하였고, 1V 전원전압에서 $2.63{\mu}A$의 전류소모를 갖는다. 칩 면적은 $0.12mm^2$이다.

This paper describes a low-power CMOS analog front-end block for UHF band RFID tag chips. It satisfies ISO/IEC 18000-6C and includes a memory block for test. For reducing power consumption, it operates with an internally generated power supply of 1V. An ASK demodulator using a current-mode schmitt trigger is proposed and designed. The proposed demodulator can more exactly demodulate than conventional demodulator with low current consumption. It is designed using a $0.18{\mu}m$ CMOS technology. Measurement results show that it can operate properly with an input as low as $0.25V_{peak}$ and consumes $2.63{\mu}A$. The chip size is $0.12mm^2$.

키워드

참고문헌

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