• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.649-651
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• 2012

본 논문에서는 Core-A를 이용한 실시간 영상 신호 처리 SoC 설계와 검증에 대해 기술한다. 영상 신호 처리를 위한 방식으로 SoC를 사용하였으며 영상 처리를 위한 ISP를 설계하였다. 영상 처리를 위한 마이크로프로세서는 코드밀도를 높이고 Verilog HDL을 사용하여 기술되어 여러 응용분야에서 최적화할 수 있는 국내에서 개발된 Core-A를 사용하였다. 본 논문에서 제안한 SoC는 Verilog HDL언어로 설계 되었고, 기본 SoC의 구조는 Core-A, AMBA Bus, ISP, Memory controller, Uart로 구성하였다. 구현된 SoC는 다양한 영상 신호 처리를 지원하여 향후 영상압축 인코더의 실시간 이미지 처리용 소스로 사용할 수 있고 신호 처리 알고리즘 검증용에도 유용하게 사용될 수 있을 것으로 보인다. 설계 검증을 위해 먼저 FPGA를 이용하여 검증하였으며 TSMC $0.18{\mu}m$ CMOS공정으로 합성한 결과 동작주파수는 50MHz, 전체 게이트 수 86.1k로 확인되었다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.10
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• pp.1169-1176
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• 2010

The RF front-end for L1/L2 dual-band Global Positioning System(GPS) receiver is presented in this paper. The RF front-end(down-converter) using low IF architecture consists of a wideband low noise amplifier(LNA), a current mode logic(CML) frequency divider and a I/Q down-conversion mixer with a poly-phase filter for image rejection. The current bleeding technique is used in the LNA and mixer to obtain the high gain and solve the head-room problem. The common drain feedback is adopted for low noise amplifier to achieve the wideband input matching without inductors. The fabricated RF front-end using $0.18{\mu}m$ CMOS process shows a gain of 38 dB for L1 and 41 dB for L2 band. The measured IIP3 is -29 dBm in L1 band and -33 dBm in L2 band, The input return loss is less than -10 dB from 50 MHz to 3 GHz. The measured noise figure(NF) is 3.81 dB for L1 band and 3.71 dB for L2 band. The image rejection ratio is 36.5 dB. The chip size of RF front end is $1.2{\times}1.35mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.25-31
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• 2009

A low power SRAM using supply voltage charge recycling (SVCR-SRAM) scheme is proposed. It divides into two SRAM cell blocks and supplies two different powers. A supplied power is $V_{DD}$ and $V_{DD}/2$. The other is $V_{DD}/2$ and GND. When N-bit cells are accessed, the charge used in N/2-bit cells with VDD and $V_{DD}/2$ is recycled in the other N/2-bit cells with $V_{DD}/2$ and GND. The SVCR scheme is used in the power consuming parts which bit line, data bus, word line, and SRAM cells to reduce dynamic power. The other parts of SRAM use $V_{DD}$ and GND to achieve high speed. Also, the SVCR-SRAM results in reducing leakage power of SRAM cells due to the body-effect. A 64K-bit SRAM ($8K{\times}8$bits) is implemented in a $0.18{\mu}m$ CMOS process. It saves 57.4% write power and 27.6% read power at $V_{DD}=1.8V$ and f=50MHz.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.727-730
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• 2005

In this paper, we propose a new current sense amplifier for low-voltage, high-speed SRAM. As a supply voltage is reduced, a sensing delay is increased owing to reduced cell read current. It causes a low-speed operation in SRAM. To overcome this problem, we present a new current sense amplifier which consists of the current-mirror type circuit with feedback structure. For demonstration, a 0.8-V, 256-Kb SRAM incorporating the proposed current sense amplifier has been designed with $0.18-{\mu}m$ CMOS technology. The simulation results show 15.6ns of the sensing delay reduction in comparison with a previous current sense amplifier and 11.5ns of the sensing delay reduction in comparison with a voltage sense amplifier.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.411-417
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• 2012

A Coarse-Fine Time-to-Digital Converter (TDC) using the single time amplifier is proposed. A vernier delay line is used to overcome process dependency and the 2-stage time amplifier is designed to have high resolution by increasing the gain of the time amplifier. Single time amplifier architecture reduces the silicon area of the TDC and alleviates mismatch effect between time amplifiers. The proposed TDC is implemented in $0.18{\mu}m$ CMOS process with the supply voltage of 1.8 V. The measured results show that the resolution of the TDC is 0.73 ps with 10-bit digital output, although highend process is not applied. The single time amplifier architecture reduces 13% of chip area compared to previous work. By reducing the supply voltage, the linearity of the TDC is enhanced and the resolution is decreased to 1.45 ps.

• Journal of Electrical Engineering and Technology
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• v.3 no.3
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• pp.430-435
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• 2008

In the paper, an algorithm called a Constraint algorithm is proposed to solve the fan-in problem occurred in ADC encoding circuits. The Flash ADC architecture uses a double-base number system (DBNS). The DBNS has known to represent the multi-dimensional logarithmic number system (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in digital signal processing (DSP) applications. The authors use the DBNS with the base 2 and 3 to represent binary output of ADC. A symmetric map is analyzed first, and then asymmetric map is followed to provide addition read DBNS to DSP circuitry. The simulation results are shown for the Double-Base Integer Encoder (DBIE) of the 6-bit ADC to demonstrate an effectiveness of the Constraint algorithm, using $0.18{\mu}\;m$ CMOS technology. The DBIE’s processing speed of the ADC is fast compared to the FAT tree encoder circuit by 0.95 GHz.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.465-470
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• 2010

The charge pump in a phase-locked loop is a key block in determining reference spurs of the VCO output signal. To reduce reference spurs, the current mismatch in the charge pump must be minimized. This paper presents a dual compensation method to reduce the current mismatch. The proposed charge pump and PLL were realized in a $0.18{\mu}m$ CMOS process. Measured current matching characteristics were achieved with less than 1.4% difference and with the current variation of 3.8% in the pump current over the charge pump output voltage range of 0.35-1.35V at 1.8V. The reference spur of the PLL based on the proposed charge pump was measured to be -71dBc.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2016.11a
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• pp.129-130
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• 2016

본 논문에서는 다중 입력의 크기를 비교하기 위한 알고리즘 및 VLSI 구조를 제안한다. 제안하는 알고리즘은 여러 입력을 동시에 비교한 후에 간단한 디지털 논리 함수를 이용하여 그 입력들 중에서 가장 큰 값(혹은 가장 작은 값)을 검출하는 방법을 제공할 수 있다. 이 방식의 단점은 하드웨어 자원이 증가하는 것인데, 이를 위해 중복된 논리 연산을 재사용하는 방법도 제안한다. 제안하고자 하는 방식은 회로 속도의 증가, 즉 지연시간의 감소에 초점을 맞추었다. 제안한 비교 알고리즘은 HDL로 설계한 후에 Magna Chip의 $0.18{\mu}m$ CMOS 라이브러리를 이용하여 구현하였다. 제안한 비교방법은 전통적인 방식에 비해서 4 및 8 입력인 경우에 약 0.5 및 1.1배 만큼 하드웨어 자원을 더 소비하면서, 약 1.5 및 1.8배 만큼 동작 주파수를 향상시킬 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.319-325
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• 2015

This paper presents an efficient vibration energy harvester with a piezoelectric (PE) cantilever. The proposed PE energy harvester increases the efficiency through minimization of hardware complexity and hence reduction of power dissipation of the circuit. Two key features of the proposed energy harvester are (i) incorporation synchronized switches with a simple control circuit, and (ii) a feed-forward buck converter with a simple control circuit. The chip was fabricated in $0.18{\mu}m$ CMOS processing technology, and the measured results indicate that the proposed rectifier achieves the efficiency of 77%. The core area of the chip is 0.2 mm2.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.