• Proceedings of the KSME Conference
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• 2005.11a
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• pp.42.1-42.1
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• 2005

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.151-151
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• 2003

최근 휴대폰용 LCD, 컴퓨터용 TFT LCD, 가정용 PDP 등 평판 디스플레이 산업의 발달에 힘입어 평판 디스플레이 장치의 구동 칩 실장 부품인 TCP(tape carrier package), COF(chip on film) 제조 산업 또한 발전하고 있다. 이들 TCP, COF는 디스플레이 장치의 경박화에 따라 보다 가는 선폭의 회로가 요구되어지는데 이를 위해 회로를 구성하는 기본소재로 얇은 두께의 동박이 사용된다. 회로기판용 동박으로는 압연동박과 전해동박이 함께 사용되어 왔으나 박막의 제조가 어려운 압연동박의 단점과 면에 수직한 주상정 조직이 발달해 있어 일반 압연 동박에 비해 접착력이 뛰어나며 전류밀도 또는 티타늄 음극 드럼 회전 속도를 조절하여 두게 조절이 용이한 전해동박의 장점으로 인해 현재 압연동박의 전해동박으로의 대체가 증가하고 있다. 전해동박의 제조공정은 크게 제박 공정과 후처리 공정으로 나눌 수 있다. 전해동박은 먼저 드럼형태의 티타늄 음극과 불용성 납 양극으로 이루어진 제박기에 고 전류를 가하여 황산구리 용액 중 구리를 티타늄 음극에 석출시킴으로서 구리 원박을 제조한 후 접착력 향상을 위한 노듈 형성, 방식, 방청, 내열성 향상 등을 위한 여러 개의 단위 셀 조합으로 이루어진 후처리 공정을 거쳐 제조된다.

• Journal of the Korean Vacuum Society
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• v.6 no.1
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• pp.20-27
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• 1997

We have investigated the formation techniques of copper thin films which would be useful for sub-quarter-micron integrated circuits. A chemical vapor deposition technology has been tried for the better side wall formation of the thin films, and a metal organic compound, named (hface)Cu(VTMS) (hexafluoroacetylacetonate vinyltrimethylsilane copper(I)) was used as the precursors. We have deposited the copper thin films on TiN and $SiO_2$substrates. The film resistivity and deposition selectivity have been measured as functions of substrate temperature and chamber pressure. Best electrical properties were obtained at $180^{\circ}C$ of substrate temperature and 0.6 Torr of chamber pressure. Under the optimum deposition conditions, polycrystalline copper structures were observed to be grown, and the deposition rate of 120 nm/min was measured. The electrical resistivity as low as 0.25$mu \Omega$.cm, and the surface roughness of 15.5 nm were also measured. These are the suitable electrical and material properties required in the sub-quarter-micron device fabrication. Also, in the substrate temperature range of 140-$250^{\circ}C$, high deposition selectivity was observed between TiN and $SiO_2$.

• Electrical & Electronic Materials
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• v.17 no.6
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• pp.11-16
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• 2004

지난 40여년간의 반도체 집적 공정의 발전에 있어서 무어(Moore)의 법칙에 의한 소자의 미세화를 달성하기 위하여, 광리소그래피(optical lithography) 기술은 꾸준히 발전하여 왔으며, 소자의 선폭이 나노스케일인 공정에서 역시, 소자 제조의 핵심기술은 리소그래피 기술을 이용한 회로의 패터닝(patterning) 기술에 달려 있다고 해도 과언이 아니다. 그러나 현재 사용되고 있는 광리소그래피는 사용하는 파장의 길이에 따른 분해능(resolution)의 한계로 인하여, 이러한 나노 스케일의 소자를 제작하기 위해서는 새로운 리소그래피 기술이 필요하다는 것이 일반적으로 인정이되고 있다.(중략)

• Journal of IKEEE
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• v.15 no.3
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• pp.205-210
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• 2011

A novel hysteresis tunable monolithic comparator circuit based on a 0.35 ${\mu}m$ CMOS process is suggested in this paper. To tune the threshold voltage of the hysteresis in the comparator circuit, two external digital bits are used with supply voltage of 3.3V. The threshold voltage of the suggested comparator circuit is controlled by 234mV by change of 4 digital control bits in the simulation, which is a close agreement to the analytic calculation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.37-42
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• 2010

A novel hysteresis tunable monolithic comparator circuit based on a $0.35{\mu}m$ CMOS process is suggested, designed, fabricated, measured and analyzed in this paper. To tune the threshold voltage of the hysteresis in the comparator circuit, two external digital bits are used with supply voltage of 3.3V.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.231-238
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• 2013

This paper describes a DC-DC converter IC for Flat Panel Displays. In case of operate LCD devices various type of DC supply voltage is needed. This device can convert DC voltage from 6~14[V] single supply to -5[V], 15[V], 23[V], and 3.3[V] DC supplies. In order to meet current and voltage specification considered different type of DC-DC converter circuits. In this work a negative charge pump DC-DC converter(-5V), a positive charge pump DC-DC converter(15V), a switching Type Boost DC-DC converter(23V) and a buck DC-DC converter(3.3V). And a oscillator, a thermal shut down circuit, level shift circuits, a bandgap reference circuits are designed. This device has been designed in a 0.35[${\mu}m$] triple-well, double poly, double metal 30[V] CMOS process. The designed circuit is simulated and this one chip product could be applicable for flat panel displays.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.7
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• pp.3474-3481
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• 2013

In this work, a new high frequency transmission line structure combined with defected ground structure (DGS) and artificial dielectric substrate (ADS) structure is proposed. DGS patterns give add the additional inductance to transmission lines and results in the increased characteristic impedance for a given line width. To the contrary, ADS presents increased capacitance and reduced line impedance. So both play a role in reducing the length of transmission lines commonly, but in preserving the line impedance complementarily. This means that the length of transmission lines can be reduced furtherly by DGS and ADS without a critical change of line width compared to the cases when one of DGS and ADS is used only. As examples, $35{\sim}100{\Omega}$ transmission lines having DGS and ADS are designed, fabricated, measured, and compared to the simulation results. A good agreement between the simulated and measured line impedances is presented. In addition, the physical lengths of the proposed transmission lines are only 55.4~76.9% of those of the normal microstrip lines for the same electrical lengths.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.139-144
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• 2016

This paper describes functional circuits of DC-DC converter IC incorporated with variable frequency PFM technique. In case of output voltage of DC-DC converter is reached setting value or output current is low then PFM switching frequency is slow down. In this work a PFM signal generator, a PFM Frequency Control Circuit, an output voltage detector and an over current protection circuits are designed. This device has been designed at a $0.35[{\mu}m]$, double poly, double metal 12[V] CMOS process.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.219-225
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• 2014

This paper describes an IC for Power Factor Correction. It can use electrical appliances which convert power from AC to DC. The power factor can be influenced not only phase difference of voltage and current but also sudden change of current waveform. This circuit enables current wave supplied to load by close to sinusoidal and minimum phase difference of voltage and current waveform. A self oscillated 10[kHz]~100[kHz] pulse signal converted to PWM waveform and it chops rectified full wave AC power which flows to load device. The multiplier and zero current detector circuit, UVLO, OVP, BGR circuits were designed. This IC has been designed and whole chip simulation use 0.5[um] double poly, double metal 20[V] CMOS process.