• Journal of IKEEE
• /
• v.25 no.2
• /
• pp.344-349
• /
• 2021

This paper proposes a structure in which Trench SiO₂ is grown inside of Super Junction IGBT P-Pillar. When observing the electric field in 3D, we checked the region where the electric field have not affected inside of the P-Pillar. The pillar region's portion resistance is varied by the breakdown voltage and size of each pillar, which reduces the size by growing SiO₂ after trenching has no field effect inside of that. At 4.5kV the same breakdown voltage, it was confirmed that the On-state voltage drop improved by about 58%, 19% compared to Field Stop IGBT and conventional Super Junction IGBT.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.11a
• /
• pp.289-292
• /
• 2004

반도체 소자의 파괴 원인으로는 주로 열, 전압, 전류, 진동 및 압력 등이 있다. 이 중에서 전압과 열을 스트레스 인자로 적용하여 가속열화 시험을 진행하였다. 전압 및 열에 의한 소자의 열화정도를 파악하기 위해 현재 상용화되어 있는 Phase Control Thyristor 중 $V_{DRM}\;=\;1500V,\;V_{BRM}\;=\;1500V, \;T_{HS}\;=\;-40{\sim}125^{\circ}C$ 정도의 사양을 가지는 소자를 사용하였다. 열화에 의한 여러 가지 변동특성 중에서 소자의 순방향 및 역방향 항복특성의 변화와 누설전류의 변화에 대해 실험을 통해 알아보았다.

• ETRI Journal
• /
• v.13 no.4
• /
• pp.10-24
• /
• 1991

본 연구에서는 기상 성장법 (VPE : vapor phase epitaxy) 으로 성장된 $n^+(Si:2X10^18cm^-3)$/$n(Si:1x10^17cm^-3)$구조의 시편 위에 SiN 과 감광막 등 식각 선택비가 서로 다른 두 물질로 보호된 소스와 드레인 사이의 게이트 형성 영역을 건식식각과 습식식각방법으로 리세스 에칭을 하여 형성한 후, 게이트를 자기정렬하여 형성시킬 수 있는 이중 리세스공정 기술을 개발하였고, 이를 통하여 전력용 MESFET 소자를 제작하였다.게이트 형성부분의 wide recess 폭은 건식식각으로 SiN을 측면식각(lateral etch) 함으로써 조절하였는데, 이 방법을 사용하여 MESFET 소자의 임계전압을 조절할 수 있고, 동시에 소스-드레인 항복전압을 30V 까지 향상시킬 수 있었다. 소스-드레인 항복전압은 wide recess 폭이 증가함에 따라, 그리고 게이트 길이가 길어짐에 따라 증가하는 경향을 보여주었다. 이 방법으로 제작한 여러종류의 MESFET 중에서 게이트 길이가 $2\mum$이고 소스-게이트 간격이 $3 \mum$인 MESFET의 전기적 특성은 최대 트랜스컨덕턴스가 120 mS/mm, 게이트 전압이 0.8V 일 때 포화드레인전류가 170~190mA/mm로 나타났다. 제작된 MESFET이 ($NH_4$)$_2$$S_x$ 용액에 담금처리될때 , 공기중에 노출된 게이트-드레인 사이의 n-GaAs층의 표면이 유황으로 보호되어 공기노출에 의한 표면 재산화막의 형성이 억제되었기 때문으로 사료된다.

• Journal of IKEEE
• /
• v.11 no.4
• /
• pp.235-238
• /
• 2007

The planar edge termination techniques of field-ring and deep junction field-ring were investigated and optimized using a two-dimensional device simulator TMA MEDICI. By trenching the field ring site which would be implanted, a better blocking capability can be obtained. The results show that the p-n junction with deep junction field-ring can accomplish near 30% increase of breakdown voltage in comparison with the conventional field-rings. The deep junctionfield-rings are easy to design and fabricate and consume same area but they are relatively sensitive to surface charge. Extensive device simulations as well as qualitative analyses confirm these conclusions.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.16 no.11
• /
• pp.1179-1185
• /
• 1991

Ultrathin Reoxidized Nitrided Oxides were formed by lamp heated rapid thermal annealing in oxyzen at temperatures of $1050^{\circ}C$-$1100^{\circ}C$ for 20, 40 seconds. The electrical characteristics of ultrathin films were evaluated by leakage current breakdown voltage. TDDB. FN tunneling. Nitridation and reoxidition condition dependence of charge trapping properties. i.e.. the flat band voltage shift $({\Delta}V_{FB})$ and the increase of charge-to-breakdown $(Q_{BD})$ induced by a high field stress where studied. As the results of analysis. rapid thermal reoxidation was achieved striking improvement of dielectric integrity, the charge to breakdown was increased and flat band voltage shift was reduced.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2003.10a
• /
• pp.377-380
• /
• 2003

An Analytic breakdown voltage model of LDMOS with internal field ring is proposed. The model is a simple analytic formula which has variables such as the dimension of drift retion, the position and doping concentration of the internal field ring, the thickness and permittivity of oxide. By comparing the results from two dimensional TCAD simulation, the proposed model explains the breakdown phenomena fairly well.

• Journal of IKEEE
• /
• v.23 no.1
• /
• pp.193-199
• /
• 2019

In this study, we have proposed a floating metal guard ring structure based on TCAD simulation in order to enhance the breakdown voltage characteristics of gallium oxide ($Ga_2O_3$) vertical high voltage switching Schottky barrier diode. Unlike conventional guard ring structures, the floating metal guard rings do not require an ion implantation process. The locally enhanced high electric field at the anode corner was successfully suppressed by the metal guard rings, resulting in breakdown voltage enhancement. The number of guard rings and their width and spacing were varied for structural optimization during which the current-voltage characteristics and internal electric field and potential distributions were carefully investigated. For an n-type drift layer with a doping concentration of $5{\times}10^{16}cm^{-3}$ and a thickness of $5{\mu}m$, the optimum guard ring structure had 5 guard rings with an individual ring width of $1.5{\mu}m$ and a spacing of $0.2{\mu}m$ between rings. The breakdown voltage was increased from 940 V to 2000 V without degradation of on-resistance by employing the optimum guard ring structure. The proposed floating metal guard ring structure can improve the device performance without requiring an additional fabrication step.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.1
• /
• pp.8-14
• /
• 2012

The device performances of n-channel MuGFET with different fin numbers and fin widths but the total effective channel width is constant have been characterized. Two kinds of Pi-gate devices with fin number=16, fin width=55nm, and fin number=14, fin width=80nm have been used in characterization. The threshold voltage, effective electron mobility, threshold voltage roll-off, inverse subthreshold slope, PBTI, hot carrier degradation, and drain breakdown voltage have been characterized. From the measured results, the short channel effects have been reduced for narrow fin width and large fin numbers. PBTI degradation was more significant in devices with large fin number and narrow fin width but hot carrier degradation was similar for both devices. The drain breakdown voltage was higher for devices with narrow fin width and large fin numbers. With considering the short channel effects and device degradation, the devices with narrow fin width and large fin numbers are desirable in the device layout of MuGFETs.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2006.05a
• /
• pp.873-877
• /
• 2006

[ $Ta_2O_5$ ] 절연막을 제조하기 위하여 ANODE OXIDATION 공정을 수립하였다. Electrolyte에서의 전압강하는 정전류 모드에서 예상되는 전압의 변화에는 영향을 주지 않지만, 정전압 모드에서 전류의 변화에 영향을 주는 것으로 나타났다. 전해질에서의 전압 강하가 음극산화 전압과 같은 값을 갖는 경우, 전류는$Ta_2O_5$/전해질 계면에서의 전압강하가 증가함에 따라 logarithmic한 형태로 변화하는 것으로 나타났다. 음극 $Ta_2O_5$ 절연막 제조공정에 있어서 전해질에서의 전압 강하는 정전류 모드에서 두께의 손실을 발생시키지만, 정전압 모드에서 다시 복원되기 때문에, 최종 두께는 음극산화 전압에 비례하는 것으로 나타났다. 음극 $Ta_2O_5$ 절연막의 전기적 특성을 조사한 결과, 항복전압은 Electrolyte의 농도와 Anodization Current에 반비례하는 것으로 나타났다. 절연막의 두께가 $1500\AA$일 때 Breakdown Voltage는 350volt. 유전상수는 29로 측정되었다.

• Journal of IKEEE
• /
• v.22 no.1
• /
• pp.180-184
• /
• 2018

Gallium oxide ($Ga_2O_3$) and silicon carbide (SiC) are the material with the wide band gap ($Ga_2O_3-4.8{\sim}4.9eV$, SiC-3.3 eV). These electronic properties allow high blocking voltage. In this work, we investigated the characteristic of $Ga_2O_3$ and 4H-SiC vertical depletion-mode metal-oxide-semiconductor field-effect transistors. We demonstrated that the blocking voltage and on-resistance of vertical DMOSFET is dependent with structure. The structure of $Ga_2O_3$ and 4H-SiC vertical DMOSFET was designed by using a 2-dimensional device simulation (ATLAS, Silvaco Inc.). As a result, 4H-SiC and $Ga_2O_3$ vertical DMOSFET have similar blocking voltage ($Ga_2O_3-1380V$, SiC-1420 V) and then when gate voltage is low, $Ga_2O_3-DMOSFET$ has lower on-resistance than 4H-SiC-DMOSFET, however, when gate voltage is high, 4H-SiC-DMOSFET has lower on-resistance than $Ga_2O_3-DMOSFET$. Therefore, we concluded that the material of power device should be considered by the gate voltage.