• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.10
• /
• pp.2253-2260
• /
• 2012

In this paper, an efficient hardware architecture is proposed for inverse transform and inverse quantization of H.264/AVC decoder. The previous inverse transform and quantization architecture has a different AC and DC coefficients decoding order. In the proposed architecture, IQ is achieved after IT regardless of the DC or AC coefficients. A common operation unit is also proposed to reduce the computational complexity of inverse quantization. Since division operation is included in the previous architecture, it will generate errors if the processing order is changed. In order to solve the problem, the division operation is achieved after IT to prevent errors in the proposed architecture. The architecture is implemented with 3-stage pipeline and a parallel vertical and horizontal IDCT is also implemented to reduce the operation cycle. As a result of analyzing the proposed ITIQ architecture operation cycle for one macroblock, the proposed one has improved by 45% than the previous one.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.2
• /
• pp.15-23
• /
• 2009

This paper presents a novel high-speed, low-complexity flexible 128/64-point $radix-2^4$ FFT/IFFT processor for the applications in high-throughput MIMO-OFDM systems. The high radix multi-path delay feed-back (MDF) FFT architecture provides a higher throughput rate and low hardware complexity by using a four-parallel data-path scheme. The proposed processor not only supports the operation of FFT/IFFT in 128-point and 64-point but can also provide a high data processing rate by using a four-parallel data-path scheme. Furthermore, the proposed design has a less hardware complexity compared with traditional 128/64-point FFT/IFFT processors. Our proposed processor has a high throughput rate of up to 560Msample/s at 140MHz while requiring much smaller hardware expenditure satisfying IEEE 802.11n standard requirements.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.6
• /
• pp.96-103
• /
• 2008

This paper proposes a new low-power and small-area Reed-Solomon decoder. The proposed Reed-Solomon decoder using a novel simplified form of the modified Euclid's algorithm can support low-hardware complexity and low-Power consumption for Reed-Solomon decoding. The simplified modified Euclid's algorithm uses new initial conditions and polynomial computations to reduce hardware complexity, and thus, the implemented architecture consisting of 3r basic cells has the lowest hardware complexity compared with existing modified Euclid's and Berlekamp-Massey architectures. The Reed-Solomon decoder has been synthesized using the $0.18{\mu}m$ Samsung standard cell library and operates at 370MHz and its data rate supports up to 2.9Gbps. For the (255, 239, 8) RS code, the gate counts of the simplified modified Euclid's architecture and the whole decoder excluding FIFO memory are only 20,166 and 40,136, respectively. Therefore, the proposed decoder can reduce the total gate count at least 5% compared with the conventional DCME decoder.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.3
• /
• pp.75-81
• /
• 2015

This paper proposed the new eight-parallel MDC FFT processor using the eight-parallel MDC architecture and the efficient scheduling scheme. The proposed FFT processor supports the 256-point FFT based on the modified radix-$2^6$ FFT algorithm. The proposed scheduling scheme can reduce the number of complex multipliers from eight to six without increasing delay buffers and computation cycles. Moreover, the proposed FFT processor can be used in OFDM systems required high throughput and low hardware complexity. The proposed FFT processor has been designed and implemented with a 90nm CMOS technology. The experimental result shows that the area of the proposed FFT processor is $0.27mm^2$. Furthermore, the proposed eight-parallel MDC FFT processor can achieve the throughput rate up to 2.7 GSample/s at 388MHz.

• Journal of IKEEE
• /
• v.24 no.3
• /
• pp.838-844
• /
• 2020

In this paper, we propose an efficient Viterbi processor using Joint Viterbi detection and decoding (JVDD) algorithm for a for bluetooth low energy (BLE) system. Since the convolutional coded Gaussian minimum-shift keying (GMSK) signal is specified in the BLE 5.0 standard, two Viterbi processors are needed for detection and decoding. However, the proposed JVDD scheme uses only one Viterbi processor by modifying the branch metric with inter-symbol interference information from GMSK modulation; therefore, the hardware complexity can be significantly reduced without performance degradation. Low-latency and low-complexity hardware architecture for the proposed JVDD algorithm was proposed, which makes Viterbi decoding completed within one clock cycle. Viterbi Processor RTL synthesis results on a GF55nm process show that the gate count is 12K and the memory unit and the initial latency is reduced by 33% compared to the modified state exchange (MSE).

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.3A
• /
• pp.265-271
• /
• 2009

This paper proposes an efficient initial frequency estimator for Digital Video Broadcasting-Second Generation (DVB-S2). The initial frequency offset of the DVB-S2 is around ${\pm}5MHz$, which corresponds to 20% of the symbol rate at 25Msps. To estimate a large initial frequency offset, the algorithm which call provide a large estimation range is required. Through the analysis of the data-aided (DA) algorithms, we find that the Mengali and Moreli (M&M) algorithm can estimate a large initial frequency offset at low SNR. Since the existing frequency estimator based on M&M algorithm has a high hardware complexity, we propose the methods to reduce the hardware complexity of the initial frequency estimator. This can be achieved by reducing the number of autocorrelators and arctangents. The proposed architecture can reduce the hardware complexity about 64.5% compared to the existing frequency estimator and has been thoroughly verified on the Xilinx Virtex II FPGA board.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.11
• /
• pp.137-141
• /
• 2007

This paper proposes a cost-effective architecture design of an angle-of-arrival (AOA) estimator based on the multiple signal identification and classification (MUSIC) algerian in UWB systems adapting Multi-band OFDM (MB-OFDM) techniques with two-receive antennas. In the proposed method, by modifying the equations of algorithm in order to remove the high computational functions, the computation power can be significantly reduced without significant performance degradation. The proposed architecture is designed and verified by Verilog HDL, and implemented into 0.13um CMOS standard cell and Xilinx FPGA circuits for the estimation of hardware complexity and computation power. From the results of the implementations, we can find that the proposed circuits reduces the hardware complexity by about 43% and the estimated computation power by about 23%, respectively, compared to the architecture employing the original MUSIC algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.41 no.11
• /
• pp.1507-1514
• /
• 2016

Full-image guided filter reflects all pixels of image in filtering by using weight propagation and two-pass model, whereas the existing guide filter is processed based on the kernel window. Therefore the computational complexity can be improved while maintaining characteristics of guide filter, such as edge-preserving, smoothing, and so on. In this paper, we propose an efficient VLSI architecture for the full-image guided filter by analyzing the data dependency, the data frequency and the PSNR analysis of the image in order to achieve enough speed for various applications such as stereo vision, real-time systems, etc. In addition, the proposed efficient scheduling enables the realtime process by minimizing the idle period in weight computation. The proposed VLSI architecture shows 214MHz of maximum operating frequency (image size: 384*288, 965 fps) and 76K of gates (internal memory excluded).

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.7 s.349
• /
• pp.50-57
• /
• 2006

Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and compared with the previous results.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.4A
• /
• pp.473-478
• /
• 2008

WAVE is a short-to-medium range communication standard that supports both public safety and private operations in roadside-to-vehicle and vehicle-to-vehicle communication environments. The core technology of physical layer in WAVE is orthogonal frequency division multiplexing (OFDM), which is sensitive to timing synchronization error. Besides, minimizing the latency in communication link is an essential characteristic of WAVE system. In this paper, a robust, low-complexity and small-latency timing synchronization algorithm suitable for WAVE system and its efficient hardware architecture are proposed. The comparison between proposed algorithm and other algorithms in terms of computational complexity and latency has shown the advantage of the proposed algorithm. The proposed architecture does not require RAM (Random Access Memory) which can affect the pipe lining ability and high speed operation of the hardware implementation. Synchronization error rate (SER) evaluation using both Matlab and FPGA implementation shows that the proposed algorithm exhibits a good performance over the existing algorithms.