DOI QR코드

DOI QR Code

Hardware Design and Implementation of Joint Viterbi Detection and Decoding Algorithm for Bluetooth Low Energy Systems

블루투스 저전력 시스템을 위한 저복잡도 결합 비터비 검출 및 복호 알고리즘의 하드웨어 설계 및 구현

  • Park, Chul-hyun (School of Electronics and Information Engineering, Korea Aerospace University) ;
  • Jung, Yongchul (School of Electronics and Information Engineering, Korea Aerospace University) ;
  • Jung, Yunho (School of Electronics and Information Engineering, Korea Aerospace University)
  • Received : 2020.09.07
  • Accepted : 2020.09.23
  • Published : 2020.09.30

Abstract

In this paper, we propose an efficient Viterbi processor using Joint Viterbi detection and decoding (JVDD) algorithm for a for bluetooth low energy (BLE) system. Since the convolutional coded Gaussian minimum-shift keying (GMSK) signal is specified in the BLE 5.0 standard, two Viterbi processors are needed for detection and decoding. However, the proposed JVDD scheme uses only one Viterbi processor by modifying the branch metric with inter-symbol interference information from GMSK modulation; therefore, the hardware complexity can be significantly reduced without performance degradation. Low-latency and low-complexity hardware architecture for the proposed JVDD algorithm was proposed, which makes Viterbi decoding completed within one clock cycle. Viterbi Processor RTL synthesis results on a GF55nm process show that the gate count is 12K and the memory unit and the initial latency is reduced by 33% compared to the modified state exchange (MSE).

본 논문에서는 검출과 복호가 결합된 효율적인 비터비 알고리즘 (joint Viterbi detection and decoding (JVDD))의 저복잡도 하드웨어 설계 및 구현 결과를 제시한다. 길쌈부호화된 GMSK 신호가 BLE 5.0 표준으로 채택 되어있으므로 검출과 복호를 위해 두개의 비터비 프로세서가 필요하다. 그러나, 제안된 JVDD 알고리즘은 GMSK에 의해서 유발된 심볼간의 간섭정보(ISI : inter-symbol interference)가 반영된 가지 메트릭 (branch metric)을 사용하여 단지 하나의 비터비 만을 사용하여도 검출과 복호 수행이 가능하며, 성능 저하 없이 복잡도 감소가 가능하다. JVDD 알고리즘을 적용한 BLE 비터비 복호기의 하드웨어 구현을 위해 효율적인 구조 설계가 수행되었다. 제안된 구조는 1 클럭 사이클 동안 복호를 완료할 수 있기 때문에 저지연 및 저면적 구현이 가능하다. 제안된 비터비 복호기는 Verilog-HDL을 이용하여 RTL 설계되었고, GF 55nm 공정을 활용하여 논리합성 및 구현되었다. 합성결과 12K 게이트 수를 포함하였으며 메모리 유닛 및 초기 지연시간은 MSE (modified state exchange) 대비 33% 감소 가능함을 확인하였다.

Keywords

References

  1. BLUETOOTH SPECIFICATION Version 5.0 $\mid$ Vol 6, Part A
  2. G. D. Forney, Jr., "Maximum-likelihood sequence estimation of digital sequences in the presence of intersymbol interference," IEEE Trans. Inform. Theory, vol.IT-18, pp.363-378, 1972. DOI: 10.1109/TIT.1972.1054829
  3. K. T. Nimisha and P. Biswagar, "Viterbi algorithm based Bluetooth low energy receiver for IoT," 2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), Bangalore, pp.978-981, 2017. DOI: 10.1109/RTEICT.2017.8256744
  4. A. James and K. S. Chan, "Joint Detector Demodulator Decoder (JDDD) over ISI Channels," 2017 IEEE 85th Vehicular Technology Conference (VTC Spring), Sydney, NSW, pp.1-5, 2017. DOI: 10.1109/VTCSpring.2017.8108440
  5. V. J. Alappat, M. Motani and C. K. Sann, "An Adaptive Joint Viterbi Detector Decoder (AJVDD)," 2016 10th International Conference on Signal Processing and Communication Systems (ICSPCS), Gold Coast, QLD, pp.1-5, 2016. DOI: 10.1109/ICSPCS.2016.7843343
  6. Kheong Sann Chan, S. S. B. Shafiee, E. M. Rachid and Yong Liang Guan, "Optimal Joint Viterbi Detector Decoder (JVDD) over AWGN/ISI channel," 2014 International Conference on Computing, Networking and Communications (ICNC), Honolulu, HI, pp.282-286, 2014. DOI: 10.1109/ICCNC.2014.6785346
  7. C. Park, Y. Jung, J. Kim and Y. Jung, "Joint Viterbi detection and decoding algorithm for bluetooth low energy systems," in Electronics Letters, vol. 56, no.6, pp.310-312, 173 2020. DOI: 10.1049/el.2019.2621
  8. D. A. F. Ei-Dib and M. I. Elmasry, "Low-power register-exchange Viterbi decoder for high-speed wireless communications," 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), Phoenix-Scottsdale, AZ, USA, pp.V-V, 2002. DOI: 10.1109/ISCAS.2002.1010809
  9. T. K. Truong, M. -. Shih, I. S. Reed and E. H. Satorius, "A VLSI design for a trace-back Viterbi decoder," in IEEE Transactions on Communications, vol.40, no.3, pp.616-624, 1992. DOI: 10.1109/26.135732
  10. G. Feygin and P. Gulak, "Architectural tradeoffs for survivor sequence memory management in Viterbi decoders," in IEEE Transactions on Communications, vol.41, no.3, pp.425-429, 1993. DOI: 0.1109/26.221067 https://doi.org/10.1109/26.221067
  11. Chun-Yuan Chu, Yu-Chuan Huang and Aneu Wu, "ower efficient low latency survivor memory architecture for Viterbi decoder," 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, pp.228-231, 2008. DOI: 10.1109/VDAT.2008.4542454
  12. Yun-Ching Tang, Do-Chen Hu, Weiyi Wei, Wen-Chung Lin and Hongchin Lin, "A memoryefficient architecture for low latency Viterbi decoders," 2009 International Symposium on VLSI Design, Automation and Test, Hsinchu, pp.335-338, 2009. DOI: 10.1109/VDAT.2009.5158163