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http://dx.doi.org/10.5573/ieie.2015.52.3.075

New Parallel MDC FFT Processor for Low Computation Complexity  

Kim, Moon Gi (Department of Electrical and Computer Engineering, Ajou University)
Sunwoo, Myung Hoon (Department of Electrical and Computer Engineering, Ajou University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.52, no.3, 2015 , pp. 75-81 More about this Journal
Abstract
This paper proposed the new eight-parallel MDC FFT processor using the eight-parallel MDC architecture and the efficient scheduling scheme. The proposed FFT processor supports the 256-point FFT based on the modified radix-$2^6$ FFT algorithm. The proposed scheduling scheme can reduce the number of complex multipliers from eight to six without increasing delay buffers and computation cycles. Moreover, the proposed FFT processor can be used in OFDM systems required high throughput and low hardware complexity. The proposed FFT processor has been designed and implemented with a 90nm CMOS technology. The experimental result shows that the area of the proposed FFT processor is $0.27mm^2$. Furthermore, the proposed eight-parallel MDC FFT processor can achieve the throughput rate up to 2.7 GSample/s at 388MHz.
Keywords
FFT; Radix-$2^6$ algorithm; MDC processor; IEEE 802.11.ac/ad; Eight-parallel;
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