The Cost-effective Architecture Design of an Angle-of-Arrival Estimator in UWB Systems

UWB 시스템에서 입사각 추정기의 효율적인 하드웨어 구조 설계

  • 이성주 (세종대학교 정보통신공학과) ;
  • 한귀범 (세종대학교 정보통신공학과)
  • Published : 2007.11.25

Abstract

This paper proposes a cost-effective architecture design of an angle-of-arrival (AOA) estimator based on the multiple signal identification and classification (MUSIC) algerian in UWB systems adapting Multi-band OFDM (MB-OFDM) techniques with two-receive antennas. In the proposed method, by modifying the equations of algorithm in order to remove the high computational functions, the computation power can be significantly reduced without significant performance degradation. The proposed architecture is designed and verified by Verilog HDL, and implemented into 0.13um CMOS standard cell and Xilinx FPGA circuits for the estimation of hardware complexity and computation power. From the results of the implementations, we can find that the proposed circuits reduces the hardware complexity by about 43% and the estimated computation power by about 23%, respectively, compared to the architecture employing the original MUSIC algorithm.

본 논문에서는 2개의 안테나를 사용하는 MB-OFDM UWB시스템에서, MUSIC 알고리듬에 기초한 입사각 추정기의 효율적인 하드웨어 구조에 대한 설계 방법을 제안한다. 제안된 방식에서는 기존 알고리듬의 연산 수식을 변형하여 기존 알고리듬에서 요구하는 복잡한 연산기능을 제거하였으며, 따라서 제안된 방식이 기존과 거의 유사한 성능을 가지면서도 하드웨어복잡도 및 연산소비전력을 크게 줄일 수 있었다. 제안된 구조는 Verilog HDL을 이용하여 설계 및 검증되었으며, 하드웨어 복잡도 및 소비전력 측정을 위해 각각 0.13um CMOS 라이브러리와 Xilinx FPGA로 구현되었다. 게이트카운트 및 소비전력을 측정한 결과, 원래의 MUSIC 알고리듬을 그대로 구현한 방식과 비교하여, 게이트카운트에서는 약 43%, 소비전력에서는 약 23%가 감소되었을 확인할 수 있었다.

Keywords

References

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