• Proceedings of the Korean Information Science Society Conference
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• 2007.06b
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• pp.482-486
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• 2007

본 논문은 기존의 O-tree 표현법을 이용한 플로어플랜 알고리즘의 결점을 보완한 새로운 알고리즘을 제안한다. 기존의 방법에선 플로어플랜의 변형을 처리하는 과정에서 몇 가지 변형을 간과하기 때문에 좋은 해를 놓치는 경우가 발생한다. 본 논문에서는 기존의 방법을 수정하여 변형을 처리하는 과정에서 블록이 들어갈 수 있는 모든 위치를 고려하였다. 그 결과 MCNC 밴치마크 회로를 이용한 실험에서 총면적이 이전의 방법에 비해 평균 3% 개선되었다.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06b
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• pp.497-501
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• 2007

BSG(Bounded Sliceline Grid)를 이용한 플로어플랜 기법은 매우 빠르고 효과적이나 모듈 사이에 빈 공간이 존재하여 필요 이상으로 면적을 넓게 차지하는데도 불구하고 그 점을 무시한채 배치 면적을 구하는 문제점이 있다. 본 논문에서는 BSG 구조를 이용한 플로어플랜 과정 중 빈 공간이 생기는 문제점을 해결하기 위해 모듈들을 좌측 또는 아래로 옮길 수 있는데 까지 옮기는 압축 기법을 추가하여 필요한 면적이 최소가 되도록 하였다. 실험 결과는 압축 기법을 사용하는 것이 사용하지 않을 때보다 최소 면적과 평균 면적 면에서 모두 개선되는 것을 보여 준다.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.11a
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• pp.203-206
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• 2008

O-tree 표현법을 이용한 기존의 플로어플랜 알고리즘은 결정적 기법에 기반한 것으로써, 회로의 각 모듈을 차례대로 삭제한 후 가장 좋은 다른 위치에 삽입하는 과정을 함으로써 해 공간을 검색해 간다. 이는 모듈을 처리하는 순서에 따라 결과가 결정되는 단점이 있다. 이런 단점을 해결하기 위해 본 논문에서는 Simulated Annealing 프레임을 이용하여 해 공간을 효과적으로 검색하는 방법을 제시한다. 이웃 해를 탐색하기 위한 플로어 플랜의 변형은 매우 단순하면서도 효과적인 두 가지 방법을 사용한다. 첫째 방법은 한 쌍의 모듈을 선택하여 상호위치를 맞바꾸는 방법이고, 둘째는 임의의 한 모듈을 선택하여 삭제한 후 삽입 가능한 모든 위치 중 임의의 한 곳에 삽입하는 연산을 사용한다. 실험 결과는 매우 고무적이다.

• Journal of the Korea Society of Computer and Information
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• v.19 no.4
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• pp.1-8
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• 2014

As cores in multi-core processors are integrated in a single chip, power density increased considerably, resulting in high temperature. For this reason, many research groups have focused on the techniques to solve thermal problems. In general, the approaches using mechanical cooling system or DTM(Dynamic Thermal Management) have been used to reduce the temperature in the microprocessors. However, existing approaches cannot solve thermal problems due to high cost and performance degradation. However, floorplan scheme does not require extra cooling cost and performance degradation. In this paper, we propose the diverse floorplan schemes in order to alleviate the thermal problem caused by the hottest unit in multi-core processors. Simulation results show that the peak temperature can be reduced efficiently when the hottest unit is located near to L2 cache. Compared to baseline floorplan, the peak temperature of core-central and core-edge are decreased by $8.04^{\circ}C$, $8.05^{\circ}C$ on average, respectively.

• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.265-274
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• 2010

As the process technology scales down and integration densities continue to increase, interconnection has become one of the most important factors in performance of recent multi-core processors. Recently, to reduce the delay due to interconnection, 3D architecture has been adopted in designing multi-core processors. In 3D multi-core processors, multiple cores are stacked vertically and each core on different layers are connected by direct vertical TSVs(through-silicon vias). Compared to 2D multi-core architecture, 3D multi-core architecture reduces wire length significantly, leading to decreased interconnection delay and lower power consumption. Despite the benefits mentioned above, 3D design technique cannot be practical without proper solutions for hotspots due to high temperature. In this paper, we propose three floorplan schemes for reducing the peak temperature in 3D multi-core processors. According to our simulation results, the proposed floorplan schemes are expected to mitigate the thermal problems of 3D multi-core processors efficiently, resulting in improved reliability. Moreover, processor performance improves by reducing the performance degradation due to DTM techniques. Power consumption also can be reduced by decreased temperature and reduced execution time.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06b
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• pp.598-603
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• 2008

Sequence-Pair(SP)는 플로어플랜을 표현하는 모델 중 하나로써, 일반적으로 SP 모델을 사용하는 플로 어프래너 (floorplanner)는 Simulated-Annealing (SA) 알고리즙을 통해 해 탐색 과정을 수행한다. SP 모델을 이용한 다양한 논문에서 플로어플랜 성능 향상을 위해 평가함수의 개선과 스케줄링 기법 향상을 모색하였으며, 평가함수의 경우 O(nlogn) 시간 알고리즘이 존재한다. 본 논문에서는 SP 모델을 이용한 SA 기법에서 SA의 해 탐색 과정 중 초기 해 탐색 시점에서 좋은 해를 빠르게 찾을 수 있는 방법을 제안한다. 제안 기법은 기존의 SA 프레임펙을 수정한 2단계 SA 알고리즘으로써 SP에 대응하는 배치를 압축하고 압축한 배치를 역변환하는 과정으로 구성된다. 실험과 결과를 통해 제안기법의 효과를 보이며, 평균적으로 동일한 SA 환경 하에서 제안기법이 최종결과 면에서 우수함을 보인다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.28-36
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• 2009

Sequence-Pair(SP) model represents the topological relation between modules. In general, SP model based floorplanners search solutions using Simulated-Annealing(SA) algorithm. Several SA based floorplanning techniques using SP model have been published. To improve the performance of those techniques they tried to improve the speed for evaluation function for SP model, to find better scheduling methods and perturb functions for SA. In this paper we propose a two phase SA based algorithm. In the first phase, white space between modules is reduced by applying compaction technique to the floorplan obtained by an SP. From the compacted floorplan, the corresponding SP is determined. Solution space has been searched by changing the SP in the SA framework. When solutions converge to some threshold value, the first phase of the SA based search stops. Then using the typical SA based algorithm, ie, without using the compaction technique, the second phase of our algorithm continues to find optimal solutions. Experimental results with MCNC benchmark circuits show that how the proposed technique affects to the procedure for SA based floorplainning algorithm and that the results obtained by our technique is better than those obtained by existing SA-based algorithms.

• Journal of the Korea Society of Computer and Information
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• v.16 no.6
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• pp.1-10
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• 2011

In designing multi-core processors, interconnection delay is one of the major constraints in performance improvement. To solve this problem, the 3-dimensional integration technology has been adopted in designing multi-core processors. The 3D multi-core architecture can reduce the physical wire length by stacking cores vertically, leading to reduced interconnection delay and reduced power consumption. However, the power density of 3D multi-core architecture is increased significantly compared to the traditional 2D multi-core architecture, resulting in the increased temperature of the processor. In this paper, the floorplan methods which change the forms of vertical placement of the core and the level-2 cache are analyzed to solve the thermal problems in 3D multi-core processors. According to the experimental results, it is an effective way to reduce the temperature in the processor that the core and the level-2 cache are stacked adjacently. Compared to the floorplan where cores are stacked adjacently to each other, the floorplan where the core is stacked adjacently to the level-2 cache can reduce the temperature by 22% in the case of 4-layers, and by 13% in the case of 2-layers.

• Journal of IKEEE
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• v.16 no.1
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• pp.45-50
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• 2012

This paper proposes the methodology to estimate the routing congestion of modern IC quickly and accurately at the early stage of the design flow. The occurrence of over-congestion in the routing process causes routing failure which then takes unnecessary time to re-design the physical design from the beginning. The precise estimation of routing congestion at the early design stage leads to a successful physical design that minimizes over-congestion which in turn reduces the total design time cost. The proposed estimation method at the block-level floorplan stage measures accurate routing congestion by using the analyzed virtual interconnections of inter/intra blocks, synthesized virtual power/ground and clock networks.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.49-58
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• 2016

In designing heterogeneous architecture based application-specific network-on-chips (NoCs), the opportunities of performance improvement would be expanded when applying asynchronous on-chip communication protocol. This is because the wire latency can be configured independently considering the wirelength of each link. In this paper, we develop the delay model of link-wire-length in asynchronous NoC and propose simulated annealing (SA) based floorplan-aware topology generation algorithm to optimize link-wirelengths. Incorporating the generated topology and the associated latency values across all links, we evaluate the performance using the floorplan-annotated sdf (standard delay format) file and RTL-synthesized gate-level netlist. Compared to TopGen, one of general topology generation algorithms, the experimental results show the reduction in latency by 13.7% and in execution time by 11.8% in average with regards to four applications.