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http://dx.doi.org/10.9708/jksci.2014.19.4.001

Analysis on the Temperature of Multi-core Processors according to Placement of Functional Units and L2 Cache  

Son, Dong-Oh (School of Electronics and Computer Engineering, Chonnam National University)
Kim, Jong-Myon (School of Electrical Engineering, University of Ulsan)
Kim, Cheol-Hong (School of Electronics and Computer Engineering, Chonnam National University)
Publication Information
Journal of the Korea Society of Computer and Information / v.19, no.4, 2014 , pp. 1-8 More about this Journal
Abstract
As cores in multi-core processors are integrated in a single chip, power density increased considerably, resulting in high temperature. For this reason, many research groups have focused on the techniques to solve thermal problems. In general, the approaches using mechanical cooling system or DTM(Dynamic Thermal Management) have been used to reduce the temperature in the microprocessors. However, existing approaches cannot solve thermal problems due to high cost and performance degradation. However, floorplan scheme does not require extra cooling cost and performance degradation. In this paper, we propose the diverse floorplan schemes in order to alleviate the thermal problem caused by the hottest unit in multi-core processors. Simulation results show that the peak temperature can be reduced efficiently when the hottest unit is located near to L2 cache. Compared to baseline floorplan, the peak temperature of core-central and core-edge are decreased by $8.04^{\circ}C$, $8.05^{\circ}C$ on average, respectively.
Keywords
Multi-core processor; Temperature; Floorplan; Hotspot;
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Times Cited By KSCI : 2  (Citation Analysis)
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