전기전자학회논문지 (Journal of IKEEE)

  • 제16권1호
  • /
  • Pages.45-50
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  • 2012
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  • 1226-7244(pISSN)
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  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
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설계 초기 단계에서 전력/클록 네트워크를 고려한 라우팅 밀집도 예측 방법론

Power/Clock Network-Aware Routing Congestion Estimation Methodology at Early Design Stage

  • 안병규 (한양대학교 전자컴퓨터통신공학과) ;
  • 정정화 (한양대학교 전자컴퓨터통신공학과)
  • Ahn, Byung-Gyu (Dept. of Electronics and Computer Engineering, Hanyang University) ;
  • Chong, Jong-Wha (Dept. of Electronics and Computer Engineering, Hanyang University)
  • 투고 : 2012.01.18
  • 심사 : 2012.03.05
  • 발행 : 2012.03.30
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초록

본 논문은 설계 흐름의 초기 단계에서 SoC의 라우팅 밀집도를 빠르고 정확하게 예측하는 방법론을 제안한다. 라우팅 과정에서 발생하는 과도한 밀집 현상은 라우팅 실패를 야기하고, 물리 설계를 처음부터 다시하게 되는 불필요한 시간을 소모하게 한다. 설계 초기단계에서 라우팅 밀집도를 정확하게 예측하는 것은 성공적인 물리 설계를 이끌어 내며, 전체 설계 시간에 소모되는 비용을 최소화시킨다. 제안된 방법은 블록 수준 플로어플랜 단계에서 블록 간/블록 내부 인터커넥트, 가상으로 합성된 파워/클록 네트워크를 사용해서 정교한 라우팅 밀집도를 예측한다.

This paper proposes the methodology to estimate the routing congestion of modern IC quickly and accurately at the early stage of the design flow. The occurrence of over-congestion in the routing process causes routing failure which then takes unnecessary time to re-design the physical design from the beginning. The precise estimation of routing congestion at the early design stage leads to a successful physical design that minimizes over-congestion which in turn reduces the total design time cost. The proposed estimation method at the block-level floorplan stage measures accurate routing congestion by using the analyzed virtual interconnections of inter/intra blocks, synthesized virtual power/ground and clock networks.

키워드

참고문헌

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