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http://dx.doi.org/10.9708/jksci.2011.16.6.001

Analysis on the Temperature of 3D Multi-core Processors according to Vertical Placement of Core and L2 Cache  

Son, Dong-Oh (School of Electronics and Computer Engineering, Chonnam National University)
Ahn, Jin-Woo (School of Electronics and Computer Engineering, Chonnam National University)
Park, Jae-Hyung (School of Computer Engineering and Information Technology, University of Ulsan)
Kim, Jong-Myon (School of Computer Engineering and Information Technology, University of Ulsan)
Kim, Cheol-Hong (School of Computer Engineering and Information Technology, University of Ulsan)
Abstract
In designing multi-core processors, interconnection delay is one of the major constraints in performance improvement. To solve this problem, the 3-dimensional integration technology has been adopted in designing multi-core processors. The 3D multi-core architecture can reduce the physical wire length by stacking cores vertically, leading to reduced interconnection delay and reduced power consumption. However, the power density of 3D multi-core architecture is increased significantly compared to the traditional 2D multi-core architecture, resulting in the increased temperature of the processor. In this paper, the floorplan methods which change the forms of vertical placement of the core and the level-2 cache are analyzed to solve the thermal problems in 3D multi-core processors. According to the experimental results, it is an effective way to reduce the temperature in the processor that the core and the level-2 cache are stacked adjacently. Compared to the floorplan where cores are stacked adjacently to each other, the floorplan where the core is stacked adjacently to the level-2 cache can reduce the temperature by 22% in the case of 4-layers, and by 13% in the case of 2-layers.
Keywords
multi-core processor; 3D integrated circuits; temperature; floorplan;
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1 T. Chiang, S. Souri, C. Chui, K. Saraswat, "Thermal Analysis of Heterogenous 3D ICs with Various Integration Scenarios," In Proceeding of International Electron Devices Meeting(IEDM) Technical Digest, pp. 31.2.1-31.2.4, Washington, DC , USA, Dec, 2001.
2 K. Banerjee, et al., "3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration," In Proceedings of the IEEE, vol. 89, no. 5, pp. 602-633, May 2001.   DOI   ScienceOn
3 H. Murata, E. S. Kuh, "Sequence Pair Based Placement Method for Hard/Soft/Pre-placed Modules," In Proceeding of International Symposium on Physical Design(ISPD), pp.167-172, Monterey, California, ,USA , April. 1998.
4 Yun-Chih Chang, Yao-Wen Chang, Guang-Ming Wu, Shu-Wei Wu, "B*-Trees: A New Representation for Non-Slicing Floorplans," In Proceeding of DAC, pp. 458-463, Los Angeles, California, USA, June, 2000.
5 W. Chu, W. Kao, "A Three-Dimensional Transient Electrothermal Simulation System for ICs," In Proceeding of THERMINIC Workshop, pp. 201- 207, Villard de Lans, France, Sept, 1995.
6 J. Cong, J. Wei, Y. Zhang, "A Thermal-Driven Floorplanning Algorithm for 3D ICs," In Proceeding of ICCAD, pp. 306-313, Dusit Resort, Pattaya Beach, Thailand, Nov, 2004
7 E. Wong, Sung Kyu Lim, "3D Floorplanning with Thermal Vias," In Proceedings of the conference on Design, Automation and Test in Europe, pp.878-883, Munich, Germany, Mar. 2006.
8 K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranaratanan, and D. Tarjan, "Temperature-Aware Microarchitecture," In Proceedings of the 30th annual international symposium on Computer architecture, pp.83-94, Apr. 2002.
9 SPEC CPU2000 Benchmarks, available at http://www.specbench.org
10 Microarchitectural Floorplanning for Thermal Management: A Technical Report, available at http://www.cs.virginia.edu/-techrep/CS-2005 -08.pdf
11 C. H. Tsai, S. M. Kang, "Cell-Level Placement for Improving Substrate Thermal Distribution," IEEE Tram. On Computer.-Aided Des, vol. 19, no. 2, pp. 253-266, Feb. 2000.   DOI   ScienceOn
12 D. C. Burger, and T. M. Austin, "The SimpleScalar tool set, version 2.0," ACM SIGARCH CAN, vol. 25, no. 3, pp. 13-25, Jun. 1997.   DOI   ScienceOn
13 D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: a framework for architectural-level power analysis and optimizations," in Proceedings of the 27th International Symposium on Computer Architecture, pp.83-94, Jun. 2000.
14 R. E. Kessler, E. J. McLellan, and D. A. Webb, "The Alpha 21264 Microprocessor Architecture," In Proceedings of the ICCD '98, pp.90-95, Austin, USA, Aug. 2002.
15 K. W. Lee, T. Nakamura, T. Ono, Y. Yamada, T. S. Nakatake, H. Murata, K. Fujiyoshi, Y. Kajitani, "Module placement on BSG-structure and IC layout applications," In Proceedings of IEEE/ACM ICCAD, pp.484-491, San Jose, USA, Nov. 1996.
16 Coskun A.K, Kahng A.B, Rosing T.S, "Temperatureand Cost-Aware Design of 3D Multiprocessor Architectures," In Proceedings of 12th Euromicro conference on Digital System Design, Architectures, Methods and Tools, pp.183-190, Patras, Greece, Aug. 2009.
17 A. K. Coskun, J. L. Ayala, D. Atienza, T. S. Rosing, and Y. Leblebici, "Dynamic Thermal Management in 3D Multicore Architectures," In Proceedings of Design, Automation & Test in Europe Conference & Exhibition, pp.1410-1415, Nice, France, Apr. 2009.
18 J. W. Joyner, Zarkesh-Ha. P, Meindl J.D, "A Stochastic Global Net-length Distribution for a Three-Dimensional System on Chip (3D-SoC)," In Proceedings of the 14th IEEE International ASIC/SOC Conference, pp.147-151, Arlington, VA, USA, Sep. 2001.
19 K. Puttaswamy, G. H. Loh, "Thermal Analysis of a 3D Die Stacked High Performance Microprocessor," In Proceedings of ACM Great Lakes Symposium on VLSI, pp. 19-24, Philadelphia, USA, 2006.
20 Hung W.-L, Link G.M, Yuan Xie, Vijaykrishnan N., Irwin M.J, "Interconnect and Thermal-aware Floorplanning for 3D Microprocessors," In Proceeding of the 7th ISQED, pp.98-104, San Jose, CA, USA, March. 2006.
21 P. N. Guo, C. K. Cheng, and T. Yoshimura, "An 0-Tree representation of non-slicing floorplan and its applications," In Proceeding of Design Automation Conference(DAC), pp.268-273, New Orleans, USA, lune. 1999.
22 S. W. Yoon, D. W. Yang, J. H. Koo, M. Padmanathan, and F. Carson, "3D TSV processes and its assembly/Packaging technology," In Proceedings of IEEE International Conference on 3D System Integration, pp.1-5, SanFrancisco, USA, Sep. 2009.
23 P. Kongetira, K. Aingaran, K. Olukotun, "Niagara: A 32-way multithreaded SPARC processor," IEEE Micro, vol. 25, no. 2, pp.21-29, March-April. 2005.   DOI   ScienceOn
24 C. Zhu, Z. Gu, L. Shang, R. P. Dick, R. Joseph, " Three-dimensional chip-multiprocessor run-time thermal management," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 8, pp. 1479-1492, Sonoma, CA, USA, Aug, 2008.   DOI   ScienceOn