• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.1
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• pp.7-12
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• 2003

The purpose of testability analysis is to estimate the difficulty of testing a stuck-at fault in logic circuits. A good testability measurement can give an early warning about the testing problem so as to provide guidance in improving the testability of a circuit. There have been researches attempting to efficiently compute the testability analysis. Conventional testability measurements, such as COP and SCOAP, can calculate the testability value of a stuck-at fault efficiently in a tree-structured circuit but may be very inaccurate for a general circuit. The inaccuracy is due to the ignorance of signal correlations for making the testability analysis linear to a circuit size. This paper proposes an efficient method for computing testability analysis, which takes into account signal correlation to obtain more accurate testability. The proposed method includes the algorithm for identifying all reconvergent fanouts in a given n circuit and the gates reachable from them, by which information related to signal correlation is gathered.

• Journal of KIISE
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• v.43 no.7
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• pp.820-826
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• 2016

There is a growing requirement for big data processing which extracts valuable information from a large amount of data. The Hadoop system employs the MapReduce framework to process big data. However, MapReduce has limitations such as inflexible and slow data processing. To overcome these drawbacks, SQL query processing techniques known as SQL-on-Hadoop were developed. Apache Tajo, one of the SQL-on-Hadoop techniques, was developed by a Korean development group. External merge sort is one of the heavily used algorithms in Tajo for query processing. The performance of external merge sort in Tajo is influenced by two parameters, sort buffer size and fanout. In this paper, we analyzed the performance of external merge sort in Tajo with various sort buffer sizes and fanouts. In addition, we figured out that there are two major causes of differences in the performance of external merge sort: CPU cache misses which increase as the sort buffer size grows; and the number of merge passes determined by fanout.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.44-48
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• 2008

According to increment of stage, the speed of changeable stage Carry-increment adder can be close to $O(\sqrt{2n})$ because the word length which is computed in stage can be lengthened by 1 bit. But the number of stage bits is increased, fan-out of carry which is inputted in stage is increased. So tile speed can be slow. This paper presents a new carry-increment adder design method to fix the number of fan-outs regardless of the number of stages. By layout simulation of 37-bit adder, the area can be Increased up to 40%, but speed improvement up to 75% can be achieved, by the proposed method, compared with a conventional method.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.381-382
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• 2012

• Proceedings of the Korean Information Science Society Conference
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• 2002.04b
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• pp.64-66
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• 2002

최근 다차원 공간색인 방법의 성능 향상을 위해 근사법을 사용하여 노드의 팬아웃을 증가시키려는 시도가 많이 행해졌다. 하지만 이러한 방법은 색인 구조의 정확성이 떨어져 불필요한 노드를 방문할 확률을 높다는 단점이 있다 본 논문에서는 정적 데이터에 대하여 노드의 팬아웃을 증가시키기 위해 하향식 STR 공간분할방법을 사용한 새로운 색인 방법을 제안한다. 제안한 방법은 공간분할방법을 사용하므로 근사법을 이용한 방법에 비해 정확성이 높을 백 아기라 하향식 계층 STR을 제안하여 STR 공간 분할방법을 효율적으로 트리 구조에 적용할 수 있도록 하였다. 이 피에도 이중분할 방법을 제안하여 점 데이터 및 사각형 데이터의 색인을 가능하게 딸 딱 아니라 사상 공간을 줄여 불필요한 노드의 방문을 막아 성능을 향상시켰다.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.41-45
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• 2018

As the size of semiconductor chip shrinks, the electronic industry has been paying close attention to fan-out wafer level packaging (FO-WLP) as an emerging solution to accommodate high input and output density. FO-WLP also has several advantages, such as thin thickness and good thermal resistance, compared to conventional packaging technologies. However, one major challenge in current FO-WLP manufacturing process is to control wafer warpage, caused by the difference of coefficient of thermal expansion and Young's modulus among the materials. Wafer warpage induces misalignment of chips and interconnects, which eventually reduces product quality and reliability in high volume manufacturing. In order to control wafer warpage, it is necessary to understand the effect of material properties and design parameters, such as chip size, chip to mold ratio, and carrier thickness, during packaging processes. This paper focuses on the effects of thickness of chip and molding compound on 12" wafer warpage after PMC of EMC using finite element analysis. As a result, the largest warpage was observed at specific thickness ratio of chip and EMC.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.1223-1224
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• 2013

• Annual Conference of KIPS
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• 2014.11a
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• pp.642-645
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• 2014

본 논문은 EAL6 수준의 공통평가기준 인증을 위해 ADV(개발) 클래스에서 ADV_INT에 대해 기술하였다. 특히, 테스트용 스마트 운영체제 소스코드 분석을 통해 구현된 내부 구조가 잘 구조화되었는지, 지나치게 복잡하지 않았는지 입증하기 위해 시도를 하였다. 다양한 소스코드 분석 도구를 통해 사이클로매틱복잡도(CyC), 정보흐름복잡도(IFC), Weighted IFC, fan-in, fan-out 등의 정보를 추출하였고, 추출된 정보를 기반으로 적용하여 수행하였다. 구조화된 정보 분석을 위해 객체지향 분석 도구를 사용한 재구조화 기법을 적용하여 수행하였다. 객체간 결합도, 팬아웃 등의 정보 등을 추출하였다. 추출된 정보를 기반으로 SW의 복잡도 및 구조적 정보를 분석한 결과 응집도 분석에 한계, TOE의 형상관리 정보 등의 부재에 따른 추출된 정보 분석의 한계, 활용된 도구의 분석 정보의 재반영 부재 및 구조적 분석 등의 한계점이 드러났다.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.41-45
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• 2015

RtMLF (Routable Molded Lead Frame) based on molded substrate has been developed to maximize advantages of both leadframe product which has high thermal and electrical performance and laminate product which accommodates more I/O count and keeps fan-in/fan-out design flexibility. Due to its structural features, RtMLF provided excellent thermal and electrical performance which was confirmed with simulation. The RtMLF samples were manufactured and its reliability analysis was done to evaluate the opportunities of the production and application.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.4
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• pp.71-81
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• 1999

We propose a new CPLD(Complexity Programmable Logic Device) technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG(Directed Acyclic Graph) type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB(Configurable Logic Block). In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time and the number of CLBs much more than the TEMPLA.