• Journal of Korea Port Economic Association
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• v.32 no.1
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• pp.123-133
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• 2016

LNG(Liquefied Natural Gas) bunkering has become an important issue with the enforcement of environment regulations in shipping industry required by the International Maritime Organization (IMO). With increased attention on LNG bunkering, many studies that focus on safety, regulation, demand forecasting, and the feasibility of LNG fueled ships have been carried out. However, most of the existing research has not included considerations of the price of LNG bunkering and its competitiveness. This paper, therefore, suggests ways to increase price competitiveness in the LNG bunkering market in the Busan Port. This paper analyzes the LNG bunkering supply mechanism by investigating various LNG bunkering terminal business in the LNG supply market. Factors that determine LNG bunkering price and its elasticity are also identified. Market players who want to operate LNG bunkering terminals in the Busan Port should introduce a merchandising trade method that is able to exclude the "Korea premium" in order to increase price competitiveness. This paper also suggests adoptable strategies such as the use of TPS (Terminal to Ship via Pipeline) type of bunkering service and the importance of location for minimizing initial investment cost.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.39-47
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• 2010

This paper proposes a fully-utilized block-based 2D DWT architecture, which consists of four 1D DWT filters with two-channel QMF PR Lattice structure. For 100% hardware utilization, we propose a new method which processes four input values at the same time. On the contrary to the image-based 2D DWT which requires large memories, we propose a block-based 2D DWT so that we only need 2MN-3N of storages, where M and N stand for filter lengths and width of the image respectively. Furthermore, the proposed architecture processes in horizontal and vertical directions simultaneously so that it computes the DWT for an $N{\times}N$ image within a period of $N^2(1-2^{-2J})/3$. Compared to existing approaches, the proposed architecture shows 100% of hardware utilization and high throughput rate. However, the proposed architecture may suffer from the long critical path delay due to the cascaded lattices in 1D DWT filters. This problem can be mitigated by applying the pipeline technique with maximum four level. The proposed architecture has been designed with VerilogHDL and synthesized using DongbuAnam $0.18{\mu}m$ standard cell.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.145-155
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Fractional Motion Estimation in 8K UHD($7680{\times}4320$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $10{\times}10$ reference data for interpolation, we design 2D cache buffer which consists of the $10{\times}10$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The gate count is 436.5Kgates. The proposed H.264/AVC Fractional Motion Estimation can support 8K UHD at 30 frames per second by running at 187MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.60-70
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• 2000

An 8$\times$8+20-bit MAC is designed with low power design methodologies at each of the system design levels. At algorithm level, a new method for multipl $y_tract operation is proposed, and it saves the transistor counts over conventional methods in hardware realization. A new Booth selector circuit using NMOS pass-transistor logic is also proposed at circuit level. It is superior to other circuits designed by CMOS in power-delay-product. And at architecture level, we adopted an ELM adder that is known to be the most efficient in power consumption, operating frequency, area and design regularity as the final adder. For registers, dynamic CMOS single-edge triggered flip-flops are used because they need less transistors per bit. To increase the operating frequency 2-stage pipeline architecture is adopted, and fast 4：2 compressors are applied in Wallace tree block. As a simulation result, the designed MAC in 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS process is operated at 200MHz, 3.3V and consumed 35㎽ of power in multiply operation, and operated at 100MHz consuming 29㎽ in MAC operations, respectively.ly.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.102-111
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD($3840{\times}2160$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $9{\times}9$ reference data for interpolation, we design 2D cache buffer which consists of the $9{\times}9$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.327-334
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• 2016

In this paper, we propose a hardware architecture of transform and quantization for high-perfornamce HEVC(High Efficiency VIdeo Coding) encoder. HEVC transform decides the transform mode by comparing RDCost to search for the best mode of them. But, RDCost is computed using the bit-rate and distortion which is computed by transform, quantization, de-quantization, and inverse transform. Due to the many calculations and encoding time, it is hard to process high resolution and high definition image in real-time. This paper proposes the method of transform mode decision by comparing sum of coefficient after transform only. We use BD-PSNR and BD-Bitrate which is performance indicator. Based on the experimental result, We confirmed that the decision of transform mode can process images with no significant change in the image quality. We reduced hardware area by assigning different values at the same output according to the transform mode and overlapping coefficient multiplied as much as possible. Also, we raise performance by implementing sequential pipeline operation. In view of the larger process that we used compared with the process of reference paper, Our design has reduced by half the hardware area and has increased performance 2.3 times.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.9
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• pp.1241-1248
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• 2010

In large-scale production of hydrogen, a PHE (Process Heat Exchanger) is a key component because the heat required to carry out the Sulfur-Iodine chemical reaction that yields hydrogen is transferred from a VHTR (Very High Temperature Reactor) by the PHE. Korea Atomic Energy Research Institute established a helium gas loop for conducting performance test of components that are used in the VHTR. In this study, as a part of high-temperature structural-integrity evaluation of a designed PHE prototype that is scheduled to be tested in the helium gas loop, we carried out high-temperature structural-analysis modeling, thermal analysis, and thermal-expansion analysis for the designed PHE prototype. An appropriate constraint condition is proposed at the end of the in-flow and out-flow pipelines of the primary and secondary coolants and the proposed constraint condition will be applied to the design of the performance-test loop setup for the designed PHE prototype.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.2 s.308
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• pp.1-11
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• 2006

In this paper, we propose a new register file architecture called the Register File Extension for Multi-words or Long-word Operation (RFEMLO) to accelerate both symmetric and asymmetric cryptographic algorithms. Based on the idea that most of cryptographic algorithms heavily use multi-words or long-word operations, RFEMLO allows multiple contiguous registers to be specified as a single operand. Thus, a single instruction can specify a SIMD-style multi-word operation or a long-word operation. RFEMLO can be applied to general purpose processors by adding instruction set for multi-words or long-word operands and functional units for additional instruction set. To evaluate the performance of RFEMLO, we use Simplescalar/ARM 3.0 (with gcc 2.95.2) and run detailed simulations on various symmetric and asymmetric cryptographic algorithms. By applying RFEMLO, we could get maximum 62% and 70% reductions in the total instruction count of symmetric and asymmetric cryptographic algorithms respectively. Also, performance results show that a speedup of 1.4 to 2.6 can be obtained in symmetric cryptographic algorithms and a speedup of 2.5 to 3.3 can be obtained for asymmetric cryptographic algorithms when we apply RFEMLO to a processor with an in-order pipeline. We also found that RFEMLO can effectively improve the performance of these cryptographic algorithms with much less cost compared to issue-width increase available in Superscalar implementations. Moreover, the RFEMLO can also be applied to Superscalar processor, leading to additional 83% and 138% performance gain in symmetric and asymmetric cryptographic algorithms.