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Design of a Block-Based 2D Discrete Wavelet Transform Filter with 100% Hardware Efficiency  

Kim, Ju-Young (Department of Information, Communication, and Electronic Engineering, The Catholic University of Korea)
Park, Tae-Guen (Department of Information, Communication, and Electronic Engineering, The Catholic University of Korea)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.47, no.12, 2010 , pp. 39-47 More about this Journal
Abstract
This paper proposes a fully-utilized block-based 2D DWT architecture, which consists of four 1D DWT filters with two-channel QMF PR Lattice structure. For 100% hardware utilization, we propose a new method which processes four input values at the same time. On the contrary to the image-based 2D DWT which requires large memories, we propose a block-based 2D DWT so that we only need 2MN-3N of storages, where M and N stand for filter lengths and width of the image respectively. Furthermore, the proposed architecture processes in horizontal and vertical directions simultaneously so that it computes the DWT for an $N{\times}N$ image within a period of $N^2(1-2^{-2J})/3$. Compared to existing approaches, the proposed architecture shows 100% of hardware utilization and high throughput rate. However, the proposed architecture may suffer from the long critical path delay due to the cascaded lattices in 1D DWT filters. This problem can be mitigated by applying the pipeline technique with maximum four level. The proposed architecture has been designed with VerilogHDL and synthesized using DongbuAnam $0.18{\mu}m$ standard cell.
Keywords
DWT; QMF filter; Lattice structure; pipeline;
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1 A. Lewis and G. Knowles, "VLSI architecture for 2D Daubechies wavelet transform without multipliers," Electron. Lett., vol.27, no.2, pp.171-173, 1997.
2 S. Paek and L. Kim, "2D DWT VLSI architecture for wavelet image processing," Electron.Lett., vol.34, no.6, pp.537-538, 1998.   DOI   ScienceOn
3 J. Kim, Y. Lee, T. Isshiki, and H. Kunieda, "Scalable VLSI architecture for lattice structure-based discrete wavelet transform," IEEE Trans. CAS-II, vol.45, no.8, pp.1031-1043, 1998.
4 C. Yu and S. Chen, "Design of an efficient VLSI architecture for 2D discrete wavelet transforms," IEEE Trans. Consumer Elect., vol.45, no.1, pp.135-140, 1999.   DOI   ScienceOn
5 F. Marino, "A Double-Face Bit-serial Architecture for the 1D Discrete Wavelet Transform," IEEE Trans. on Circuits & Systems II-Analog & Digital Signal Preocessing, vol.47, no.1, pp.65-71, 2000.   DOI   ScienceOn
6 T. Park and S. Jung, "High Speed Lattice Based VLSI Architecture of 2D Discrete Wavelet Transform for Real-Time video Signal Processing," IEEE Trans. on Consumer Electronics, vol.48, no.4, pp.1026-1032, 2002.
7 P. Vaidyanathan, "Multirate systems and filter banks", Prentice-Hall, 1993.
8 T. Ryan, L. Sanders, H. Fisher, and A. Iverson, "Image compression by texture modeling in the wavelet domain," IEEE Trans. Image Process., vol.5, pp.26-36, 1996.   DOI   ScienceOn
9 Iain E. G. Richardson, "H.264 and MPEG-4 Video Compression," John Willey & Sons, 2003.
10 S. Mallat, "A theory for multiresolution signal decomposition: The wavelet representation," IEEE Trans. Pattern Anal. and Machine Intell., vol.11, no.7, pp.674-693, 1989.   DOI   ScienceOn
11 A. Skodras, C. Christopoulos, and T. Ebrahimi, "JPEG2000: The Upcoming Still Image Compression Standard," Proceedings of 11th conf. of Pattern Recognition, pp.359-366, 2000.
12 M. Vishwanath, R. Owens, and M. Irwin, "VLSI architectures for the discrete wavelet transform," IEEE Trans. CAS-II, vol.42, no.5, pp.305-316, 1995.
13 T. Denk and K. Pahri, "VLSI architectures for Lattice structure based orthogonal discrete wavelet transform," IEEE Trans. CAS-II, vol.44, no.2, pp.129-132, 1997.