• Journal of Korea Society of Industrial Information Systems
• /
• v.20 no.4
• /
• pp.39-45
• /
• 2015

In this paper, variable rate CDR(Clock and Data Recovery) circuit adopting blind oversampling architecture is presented. The clock recovery circuit is implemented by using wide range voltage controlled oscillator and band selection method and the data recovery circuit is designed to digital circuit used majority voting method in order to low power and small area. The designed low power variable clock and data recovery is implemented by wide range voltage controlled oscillator and digital data recovery circuit. The designed variable rate CDR is operated from 10 bps to 2 Mbps. The total power consumption is about 4.4mW at 1MHz clock. The supply voltage is 1.2V. The designed die area is $120{\mu}m{\times}75{\mu}m$ and this circuit is fabricated in $0.13{\mu}m$ CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.3
• /
• pp.555-562
• /
• 2008

In this paper we proposed a practical low-power design technique using clock-gating in RTL. An efficient low-power methodology is that a high-level designer analyzes a generic system and designs a controller for clock-gating. Also the desirable flow is to derive clock-gating in normal synthesis process by synthesis tool than to insert directly gate to clock line. If low-power is considered in coding process, clock is gated in coding process. If not considered, after analyzing entire operation. clock is Bated in periods of holding data. After analyzing operation for clock-gating, a controller was designed for it, and then a low-power circuit was generated by synthesis tool. From result, we identified that the consumed power of register decreased from 922mW to 543mW, that is the decrease rate is 42%. In case of synthesizing the test circuit using synthesizer of Power Theater, it decreased from 322mW to 208mW (36.5% decrease).

• Electronics and Telecommunications Trends
• /
• v.24 no.6
• /
• pp.110-120
• /
• 2009

비동기식 회로는 전역 클록이 없이 모듈끼리의 핸드셰이크 프로토콜에 의해 데이터를 동기화하고, 전송하는 회로로 전역 클록에 기반한 동기식 회로에 비해 전역 클록으로 인한 문제점들, 예를 들면, 타이밍 종결 문제, 전력 소모 문제, 다중 클록 도메인 설계 문제 등에서 이점을 갖는다. 최근에는 이 두 가지 회로의 장점을 모아 서로 다른 클록에 기반한 비교적 작은 규모의 동기식 모듈을 기반으로 모듈끼리의 데이터 전송을 비동기식으로 수행하는 GALS 구조도 많이 연구되고 있다. 본 고에서는 이러한 비동기식 회로를 위한 설계 방식을 설명하기 위해 먼저, 비동기식 회로의 특성과 설계 동향, 설계 방식에 영향을 미치는 핸드셰이크 프로토콜 및 지연 모델을 소개한다. 그리고, 크게 세가지의 설계 방식을 간단한 예제를 통해 설명한다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.4 no.2
• /
• pp.83-87
• /
• 2011

Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. Almost systems require that the clock length is required prior to scheduling, the best value of the clock can be found only after evaluating different schedules. In this study, we presents a scheduling method that works simultaneously with synthesis by selecting a clock from a chainable operation set. Our scheduling algorithm is based on list scheduling and executes chaining considering bit level delays based on selected clock period. Experimental results show that our method improves the performance by 18 percent.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.1
• /
• pp.97-103
• /
• 2014

In this paper, a clock-data recovery using a 1/8-rate phase detector is proposed. The use of a conventional full or half-rate phase detector requires relatively higher frequency of a recovered clock, which is a burden on the design of a sampling circuit and a VCO. In this paper, a 1/8-rate phase detector is used to lower the frequency of the recovered clock and a linear equalizer is used as a input circuit of a phase detector to reduce the jitter of the recovered clock. A test chip fabricated in a 0.13-${\mu}m$ CMOS process is measured at 1.5-GHz for a 3-Gb/s PRBS input and 1.2-V power supply.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.6
• /
• pp.446-455
• /
• 2001

In this paper, the precise synchronized clock generator using GPS receiver is presented. The GPS receiver provides a synchronized IPPS signal which guaranties a reliable standard time mark. This signal allows us to do time synchronization and correct the time step. We designed and implemented the precise synchronized clock generator based on DPLL in order to generate a high-resolution clock from a low-cost inaccurate oscillator with ALTERA FLEX EPM6016TC144-3. We also implemented a hardware unit and proved that the unit provides 1MHz clock output which had a high resolution and accuracy when it was combined with GPS receiver.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.10 s.352
• /
• pp.28-33
• /
• 2006

An integrated 3.125Gbps clock and data recovery (CDR) circuit is presented. The circuit does not need a reference clock. It has a phase and frequency detector (PFD), which incorporates a bang-bang type 4X oversampling PD and a rotational frequency detector (FD). It also has a ring oscillator type VCO with four delay stages and three zero-offset charge pumps. With a proposed PD and m, the tracking range of 24% can be achieved. Experimental results show that the circuit is capable of recovering clock and data at rates of 3.125Gbps with 0.18 um CMOS technology. The measured recovered clock jitter (p-p) is about 14ps. The CDR has 1.8volt single power supply. The power dissipation is about 140mW.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.4
• /
• pp.1-8
• /
• 2004

A novol clock distribution scheme is proposed for high-speed and low-power digital system to minimize clock skew and reduce dynamic power consumption. This scheme has ideal zero-skew characteristic by using folded clock lines (FCL) and phase blending circuit. For analyzing suitable line structures to FCLs, microstrip line and coplanar line are placed with folded clock lines. Simulation results show that the maximum clock-skew between two receivers located 10mm apart is less than lops at 1㎓ and the maximum clock-skew between two receivers located 20mm apart is less than 60ps at 1㎓. Also the results show that the minimum skews of clock signals regardless of process, voltage, and temperature variation are invariant.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.2
• /
• pp.130-134
• /
• 2008

This paper presents a clock and data recovery(CDR) using a quarter-rate technique. The proposed CDR helps reduce the VCO frequency and is thus advantageous for high speed application. It can achieve a low jitter operation and extend the pull-in range without a reference clock. The CDR consists of a quarter-rate bang-bang type phase detector(PD) quarter-rate frequency detector(QRFD), two charge pumps circuits(CPs), low pass filter(LPF) and a ring voltage controlled oscillator(VCO). The Proposed CDR has been fabricated in a standard $0.18{\mu}m$ 1P6M CMOS technology. It occupies an active area $1{\times}1mm^2$ and consumes 98 mW from a single 1.8 V supply.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.5
• /
• pp.893-898
• /
• 2017

A TDC(Time-to-Digital Converter) of counter-type is designed by $0.18{\mu}mCMOS$process and the supply voltage is 1.5 volts. The converted error of maximum $T_{CK}$ is occurred by the time difference between the start signal and the clock when the period of clock is $T_{CK}$ in the conventional TDC. And the converted error of -$T_{CK}$ is occurred by the time difference between the stop signal and the clock. However in order to compensate the disadvantage of the conventional TDC the clock is generated within the TDC circuit and the clock is synchronized with the start and stop signals. In the designed TDC circuit the conversion error is not occurred by the difference between the start signal and the click and the magnitude of conversion error is reduced (1/2)$T_{CK}$ by the time difference between the stop signal and the clock.