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3.125Gbps Reference-less Clock/Data Recovery using 4X Oversampling  

Lee, Sung-Sop (Hynix Semiconductor)
Kang, Jin-Ku (School of Electronic and Electrical Engineering Inha University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.43, no.10, 2006 , pp. 28-33 More about this Journal
Abstract
An integrated 3.125Gbps clock and data recovery (CDR) circuit is presented. The circuit does not need a reference clock. It has a phase and frequency detector (PFD), which incorporates a bang-bang type 4X oversampling PD and a rotational frequency detector (FD). It also has a ring oscillator type VCO with four delay stages and three zero-offset charge pumps. With a proposed PD and m, the tracking range of 24% can be achieved. Experimental results show that the circuit is capable of recovering clock and data at rates of 3.125Gbps with 0.18 um CMOS technology. The measured recovered clock jitter (p-p) is about 14ps. The CDR has 1.8volt single power supply. The power dissipation is about 140mW.
Keywords
Clock and data recovery (CDR); frequency detector; Phase detector; 4X Oversampling; Charge Pump;
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Times Cited By KSCI : 1  (Citation Analysis)
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