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http://dx.doi.org/10.5573/ieie.2014.51.1.097

A Clock-Data Recovery using a 1/8-Rate Phase Detector  

Bae, Chang-Hyun (Department of Electronics and Computer Engineering, Hanyang University)
Yoo, Changsik (Department of Electronics and Computer Engineering, Hanyang University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.51, no.1, 2014 , pp. 97-103 More about this Journal
Abstract
In this paper, a clock-data recovery using a 1/8-rate phase detector is proposed. The use of a conventional full or half-rate phase detector requires relatively higher frequency of a recovered clock, which is a burden on the design of a sampling circuit and a VCO. In this paper, a 1/8-rate phase detector is used to lower the frequency of the recovered clock and a linear equalizer is used as a input circuit of a phase detector to reduce the jitter of the recovered clock. A test chip fabricated in a 0.13-${\mu}m$ CMOS process is measured at 1.5-GHz for a 3-Gb/s PRBS input and 1.2-V power supply.
Keywords
Phase detector; CDR; Linear equalizer;
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Times Cited By KSCI : 1  (Citation Analysis)
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