• Journal of the Institute of Electronics Engineers of Korea CI
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• v.37 no.5
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• pp.45-53
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• 2000

This paper presents an analysis of the dynamical behavor in the chaotic neuron fabricated using 0.8${\mu}{\textrm}{m}$ single poly CMOS technology. An approximated empirical equation models for the sigmoid output function and chaos generative block of the chaotic neuron are extracted from the measurement data. Then the dynamical responses of the chaotic neuron such as biurcation diagram, frequency responses, Lyapunov exponent, and average firing rate are calculated with numerical analysis. In addition, we construct the chaotic neural networks which are composed of two chaotic neurons with four synapses and obtain bifurcation diagram according to synaptic weight variation. And results of experiments in the single chaotic neuron and chaotic neural networks by two neurons with the $\pm$2.5V power supply and sampling clock frequency of 10KHz are shown and compared with the simulated results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.333-341
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• 2015

In this paper, a 0.5~4 GHz frequency synthesizer having good phase noise performance is proposed. Wideband output frequencies of the synthesizer were synthesized using DDS(Direct Digital Synthesizer) and analog direct frequency synthesis technology in order to obtain fast settling time. Also in order to get good phase noise performance, 2.4 GHz DDS clock was generated by VCO(Voltage Controlled Oscillator) which was locked by the 100 MHz reference oscillator using SPD(Sample Phase Detector). The phase noise performance of wideband frequency synthesizer was estimated and the results were compared with the measured ones. The measured phase noise of the frequency synthesizer was less then -121 dBc @ 100 kHz at 4 GHz.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.1
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• pp.27-32
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• 2019

This study describes the design and implementation of a simulated signal generator to demonstrate the performance of VHF band radar for the detection of small targets in RCS(Radar Cross Section). The transmission and reception antenna beam widths used in the simulated signal generating apparatus may be large, which may cause problems in the degree of isolation. Interference signal immunity and isolation characteristics are improved by considering operating conditions of VHF radar to solve isolation of antennas. Simulated signal generator performs the following: VHF radar transmission and reception correction, simulation signal generation, target Doppler, RCS and distance simulation, remote control, and GPS clock synchronization function. After the fabrication of the simulated signal generator, the main characteristics, such as the output characteristics and the reflection signal simulations, were tested. When the microwave radar assembly is completed in the future, it will be utilized for the performance evaluation of VHF radar.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.39-45
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• 2004

This paper describes the design and implementation of Serial ATA physical layer and performance measurement. It is composed of tranceiver circuit that has the NRZ data stream with +/-250㎷ voltage level and 1.5Gbps data rate, transmission PLL circuit, clock ＆ data recovery circuit, serializer/deserializer circuit and OOB(Out Of Band) generation/detection circuit. We implement the verification of the silicon chip with 0.18${\mu}{\textrm}{m}$ Standard CMOS process. It can be seen that all of the blocks operate with no errors but the data transfer rate is limited to the 1.28Gbps even this should support 1.5Gbps data transfer rate.

• Journal of the Korean Institute of Intelligent Systems
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• v.25 no.4
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• pp.405-411
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• 2015

This paper sugg ests speed measurement and control system desig n methods to drive the Wheel-in Motor that is transfer rotational force to the hub of the wheel and drives it directly. The dsPIC30F2010 16 bit microprocessor specified to motion controller is used as a intelligent controller. The minimum functions of dsPIC30F2010, system clock, PWM output, I/O, timer, communication, applicable to motor control are used and operating characteristics of hall signal measurement and control software functions are tested. Also the algorithm including PDFF speed control program was implemented using this software functions and show the experimental results..

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.12
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• pp.1243-1250
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• 2014

In this paper, a wideband DDS module covering the frequency range from 0.5 to 1.1 GHz was designed and fabricated. The clock frequency of the DDS was selected 2.4 GHz in order for 600 MHz output bandwidth. Multiple spurious cancelling signals having same amplitude and $180^{\circ}$ phase difference compared to the spurious were created at the additional path and added to the output signal within DDS for the spurious performance improvement. The fabricated DDS module showed better spurious performance than the commercial DDS one more than 10 dB and frequency tuning time was 340 ns below.

• Journal of Advanced Navigation Technology
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• v.13 no.3
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• pp.337-343
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• 2009

In this paper, we proposed a burst mode symbol timing recovery unit that is applicable to the VDL Mode-2 using D8PSK modulation. A method that IIR loop filter is used to minimize symbol timing error is hard to apply to burst mode because its convergence time is long. That is, the fast convergence property is important. In this paper, the proposed method takes one sample which has maximum symbol power after the initial synchronization has been achieved by using preambles. The main principle of operation is that the unit moves one sample clock to advance or retard according to symbol power. We verify that the proposed method is operated well in ${\pm}100$ ppm or greater through the test results between Australia ADS Corp. transmitter and the designed receiver.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.923-926
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• 2007

유비쿼터스 환경에서 소형, 저전력의 임베디드 시스템은 저가로 구성되는 시스템이라는 특성으로 인해 넓고 다양한 지역에 분포될 수 있고 분포 시킬 시스템의 개수와 설치 방법등에 있어 큰 유연성을 가지고 있어 그 활용에 있어 매우 큰 잠재적인 요소를 보유하고 있다. 이러한 시스템에 채용되는 마이크로컨트롤러는 매우 제한된 메모리 용량과 낮은 클럭속도, 낮은 레벨의 연산 성능을 가지는게 일반적이다. 본 논문에서의 마이크로 컨트롤러를 위한 영상 촬영 및 압축 시스템은 이러한 소형의 마이크로 컨트롤러를 사용한 소형의 저전력 임베디드 시스템에서 사용하기 위한 목적의 영상 촬영 및 압축을 위한 시스템이다. 본 시스템은 영상을 촬영하고 촬영된 영상을 JPEG로 압축하며 이를 내부 메모리에 보관함으로써 저사양의 마이크로컨트롤러를 가지는 시스템과 낮은 데이터 전송률을 가지는 통신 환경에서도 이미지 기반의 서비스를 제공할 수 있는 환경을 제공하면서 동시에 매우 소형의 시스템으로 배터리 동작 기반의 저전력 시스템을 위한 설계로 유비쿼터스 환경의 구성에 매우 유용한 기능을 제공한다.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.3
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• pp.290-295
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• 2005

The incremental encoder has been mostly used to measure the speed and position of the motor. As the output signals of encoder are high frequency digital signals, they have much influence on radiation noises due to switching of the power semiconductor circuits. It is so difficult to suppress the noises with the conventional LPF. In this paper, the hardware digital filter for suppressing noises in the output signals of the encoder signals is developed. As both the clock frequency and counter in the digital filter for encoder are easily adjusted according to the kinds of noises, any noises in the encoder can be entirely eliminated. The performance of the digital filter has been verified by simulation and experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.10
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• pp.2136-2149
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• 1997

This paper describes RISC core that has been designed for embedded and protable applications such as PDA or PCS. This RISC processor offers low power consumption and fast context switching. Processor performance is improved by using conditional instruction execution, block data transfer instruction, and multiplication instruction. This architecture is based on RISC principles. The processor adopts 3-stage instruction execution pipeline and has achieved single cycle execution using a 2-phase 40MHz clock. This results in a high instruction throughput and real-time interrupt response. This chip is implemented with $0.6{\mu}m$ triple metal CMOS technology and consists of about 88K transistors. The estimated power dissipation is 179mW.