• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.12
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• pp.939-943
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• 2011

In this paper, reliability of the two sandwiched MIM capacitors of $Al_2O_3-HfO_2-Al_2O_3$ (AHA) and $SiO_2-HfO_2-SiO_2$ (SHS) with hafnium-based dielectrics was analyzed using two kinds of voltage stress; DC and AC voltage stresses. Two MIM capacitors have high capacitance density (8.1 fF/${\mu}m^2$ and 5.2 fF/${\mu}m^2$) over the entire frequency range and low leakage current density of ~1 nA/$cm^2$ at room temperature and 1 V. The charge trapping in the dielectric shows that the relative variation of capacitance (${\Delta}C/C_0$) increases and the variation of voltage linearity (${\alpha}$/${\alpha}_0$) gradually decreases with stress-time under two types of voltage stress. It is also shown that DC voltage stress induced greater variation of capacitance density and voltage linearity than AC voltage stress.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1064-1073
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• 2013

In this paper, a compact 370 W high efficiency GaN(Gallium Nitride) HEMT(High Electron Mobility Transistor) power amplifier(PA) using internal harmonic manipulation circuits is presented for cellular and L-band. We employed a new circuit topology for simultaneous high efficiency matching at both fundamental and 2nd harmonic frequency. In order to minimize package size, new 41.8 mm GaN HEMT and two MOS(Metal Oxide Semiconductor) capacitors are internally matched and combined package size $10.16{\times}10.16{\times}1.5Tmm^3$ through package material changes and wire bonded in a new package to improve thermal resistance. When drain biased at 48 V, the developed GaN HEMT power amplifier has achieved over 80 % Drain Efficiency(DE) from 770~870 MHz and 75 % DE at 1,805~1,880 MHz with 370 W peak output power(Psat.). This is the state-of-the-art efficiency and output power of GaN HEMT power amplifier at cellular and L-band to the best of our knowledge.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1154-1162
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• 2016

This paper proposes a fast-transient digital LDO(Low dropout) regulator with binary-weighted current control technique. Conventional digital LDO takes a long time to stabilize the output voltage, because it controls the amount of current step by step, thus ringing problem is generated. Binary-weighted current control technique rapidly stabilizes output voltage by removing the ringing problem. When output voltage reliably reaches the target voltage, It added the FRZ mode(Freeze) to stop the operation of digital LDO. The proposed fast response digital LDO is used with a slow response DC-DC converter in the system which rapidly changes output voltage. The proposed digital controller circuit area was reduced by 56% compared to conventional bidirectional shift register, and the ripple voltage was reduced by 87%. A chip was implemented with a $0.18{\mu}F$ CMOS process. The settling time is $3.1{\mu}F$ and the voltage ripple is 6.2mV when $1{\mu}F$ output capacitor is used.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.591-600
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• 2010

In this paper, three kinds of 24 GHz low-power CMOS cross-coupled voltage controlled oscillators are designed and fabricated for a short-range radar applications using TSMC 0.13 ${\mu}m$ CMOS process. The basic CMOS crosscoupled voltage controlled oscillator is designed for oscillating around a center frequency of 24.1 GHz and subthreshold oscillators are developed for low power operation from it. A double resonant circuit is newly applied to the subthreshold oscillator to improve the problem that parasitic capacitance of large transistors in a subthreshold oscillator can push the oscillation frequency toward lower frequencies. The fabricated chips show the phase noise of -101~-103.5 dBc/Hz at 1 MHz offset, the output power of -11.85~-15.33 dBm and the frequency tuning range of 475~852 MHz. In terms of power consumption, the basic oscillator consumes 5.6 mW, while the subthreshold oscillator does 3.3 mW. The subthreshold oscillator with the double resonant circuit shows relatively lower power consumption and improved phase noise performance while maintaining a comparable frequency tuning range. The subthreshold oscillator with double resonances has FOM of -185.2 dBc based on 1 mW DC power reference, which is an about 3 dB improved result compared with the basic oscillator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.1-6
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• 2008

In this paper, millimeter-wave broadband MHEMT (Metamorphic High Electron Mobility Transistor) cascode amplifiers were designed and fabricated. The $0.1{\mu}m$ InGaAs/InAlAs/GaAs MHEMT was fabricated for cascode amplifiers. The DC characteristics of MHEMT are 670 mA/mm of drain current density, 588 mS/mm of maximum transconductance. The current gain cut-off frequency($f_T$) is 139 GHz and the maximum oscillation frequency($f_{max}$) is 266 GHz. To prevent oscillation of the designed cascode amplifiers, a parallel resistor and capacitor were connected to the drain of common gate device. By using the CPW (Coplanar Waveguide) transmission line, the cascode amplifier was designed and matched for the broadband characteristics. The designed amplifier was fabricated by the MHEMT MMIC process that was developed through this research. As the results of measurement, the amplifier was obtained 3 dB bandwidth of 50.37 GHz between 20.76 to 71.13 GHz. Also, this amplifier represents the S21 gain with the average 7.07 dB gain in bandwidth and the maximum gain of 10.3 dB at 30 GHz.

• Journal of the Korean Vacuum Society
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• v.14 no.1
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• pp.49-57
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• 2005

The characteristics of current and voltage in a basic discharge experiment are investigated for a cold cathode fluorescent lamp with ballast capacitors attached at both ends of lamp and for a capacitive coupled external electrode fluorescent lamp. In the current-voltage characteristics for a cold cathode fluorescent lamp except ballast capacitors, it is shown that the typical glow discharge with the cathode fall follows after the dark current and Townsend firing discharge. However, in the characteristics for a cold cathode fluorescent lamp including ballast capacitors, the current increases as the voltage increases in the glow discharge region without representing a cathode fall since the most voltage is loaded at two capacitors. The characteristics for the external electrode fluorescent lamp shows the same as that of the cold cathode fluorescent lamp in the respect of glow discharge characters, and the external electrode itself roles the ballast capacitor.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.10 s.352
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• pp.90-97
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• 2006

We report our research work on the millimeter-wave broadband amplifier integrating the shunt peaking technology with the cascode configuration. The millimeter-wave broadband cascode amplifier on MIMIC technology was designed and fabricated using $0.1{\mu}m\;{\Gamma}-gate$ GaAs PHEMT, CPW, and passive library. The fabricated PHEMT has shown a transconductance of 346.3 mS/mm, a current gain cut off frequency ($f_T$) of 113 GHz, and a maximum oscillation frequency ($f_{max}$) of 180 GHz. To prevent oscillation of designed cascode amplifier, a parallel resistor and capacitor were connected to drain of common-gate device. For expansion of the bandwidth and flatness of the gain, we inserted the short stub into bias circuits and the compensation transmission line between common-source device and common-gate device, and then their lengths were optimized. Also, the input and output stages were designed using the matching method to obtain the broadband characteristic. From the measurement, we could confirm to extend bandwidth and flat gain by integrating the shunt peaking technology with the cascode configuration. The cascode amplifier shows the broadband characteristic from 19 GHz to 53.5 GHz. Also, the average gain of this amplifier is about 6.5 dB over the bandwidth.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.6-12
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• 2010

A sigma-delta modulator based class-D audio amplifier is presented. Parallel digital input is serialized to two-bit output by a fourth-order digital sigma-delta noise shaper. The output of the digital sigma-delta noise shaper is applied to a fourth-order analog sigma-delta modulator whose three-level output drives power switches. The pulse density modulated (PDM) output of the power switches is low-pass filtered by an LC-filter. The PDM output of the power switches is fed back to the input of the analog sigma-delta modulator. The first integrator of the analog sigma-delta modulator is a hybrid of continuous-time (CT) and switched-capacitor (SC) integrator. While the sampled input is applied to SC path, the continuous-time feedback signal is applied to CT path to suppress the noise of the PDM output. The class-D audio amplifier is fabricated in a standard $0.13-{\mu}m$ CMOS process and operates for the signal bandwidth from 100-Hz to 20-kHz. With 4-${\Omega}$ load, the maximum output power is 18.3-mW. The total harmonic distortion plus noise and dynamic range are 0.035-% and 80-dB, respectively. The modulator consumes 457-uW from 1.2-V power supply.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.1
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• pp.77-83
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• 2011

In this thesis, 50W Doherty amplifier was designed and implemented for Beyond 3G's repeater and base-station. Auxiliary amplifier of doherty amplifier was implemented by Gate bias control circuit. Though gate bias control circuit solved auxiliary's bias problem, output characteristics of doherty amplifier was limited. To enhance the output characteristic relativize Drain control circuit And To improve power efficiency make 3-way Doherty power amplifier. therefore, 3-way GDCD (Gate and Drain bias Control Doherty) power amplifier is embodied to drain bias circuit for General Doherty power amplifier. The 3-way GDCD power amplifier composed of matching circuit with chip capacitor and micro strip line using FR4 dielectric substance of specific inductive capacity(${\varepsilon}r$) 4.6, dielectric substance height(H) 30 Mills, and 2.68 Mills(2 oz) of copper plate thickness(T). Experiment result satisfied specification of amplifier with gains are 57.03 dB in 2.11 ~ 2.17 GHz, 3GPP frequency band, PEP output is 50.30 dBm, W-CDMA average power is 47.01 dBm, and ACLR characteristics at 5MHz offset frequency band station is -40.45 dBc. Especially, 3-way DCHD power amplifier showed excellence efficiency performance improvement in same ACLR than general doherty power amplifier.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.