• The Journal of the Korea Contents Association
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• v.10 no.12
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• pp.10-17
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• 2010

In this paper, we design digital D-PHY link chip controling DSI (Display Serial Interface) that meets MIPI (Mobile Industry Processor Interface) standard. The D-PHY supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. For low power consumption, the unit blocks in digital D-PHY are optionally switched using the clock gating technique. The proposed low power digital D-PHY is simulated and compared with conven tional one about power consumption on each transaction mode. As a result, power consumptions of TX, RX, and total in HS mode decrease 74%, 31%, and 50%, respectively. In LP mode, power reduction rates of TX, RX, and total are 79%, 40%, and 51.5%, separately. We implemented the low power MIPI D-PHY digital chip using $0.13-{\mu}m$ CMOS process under 1.2V supply.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.28 no.3
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• pp.106-111
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• 2018

Halide perovskite nanocrystals have become attractive for LED applications due to their high color purity and excellent luminescent properties. $CsPbX_3$ (X = I, Br, and Cl) nanocrystals were synthesized by hot-injection method and the emission wavelength was controlled by changing the composition of halide ion. Green- and red-emitting films were fabricated using a polymer binder. The outstanding optical properties of the synthesized nanocrystals and fabricated films were confirmed. The wLED designed by green- and red-emitting perovskite nanocrystal films on blue InGaN LED was characterized.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.77-83
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• 2004

In low-power VLSI systems, it is effective to suppress leakage current by shutting down megablocks in idle states. Recently, multi-threshold voltage CMOS (MTCMOS) is widely accepted to shutdown power supply. However, it requires short wake-up time as operating frequency increases. This causes large current surge during wake-up process, and it often leads to system malfunction due to severe Power line noise. In this paper, a novel wake-up scheme is proposed to solve this problem. It exploits pipelined wake-up strategy in several stages that reduces maximum current on the power line and its corresponding power line noise. To evaluate its efficiency, the proposed scheme was applied to a multiplier block in the Compact Flash memory controller chip. Power line noise in shutdown and wake-up process was simulated and analyzed. From the simulation results, the proposed scheme was proven to greatly reduce the power line noise compared with conventional schemes.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.5
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• pp.477-485
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• 2002

In this paper, we present an efficient hardware architecture for the H.263 video codec and its VLSI implementation. This architecture is based on the unified interface by which internal hardware engines and an internal RISC processor are connected one another. The unified interface enables the modular design of internal blocks, efficient hardware/software partitioning, and pipelined paralled operations. The developed VLSI supports the H.263 version 2 profile 3 @ level 10, and moreover, both the control protocol H.245 and the multiplexing protocol H.223. Therefore, it can be used for the complete ITU-T H.324 or 3GPP 3G 324M multimedia processor with the help of an external audio codec. Simultaneous encoding and decoding of QCIF format images at a rate greater than 15 frames per second is achieved at 40 MHz clock frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.51-58
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• 2016

As semiconductor technology has developed, device performance has been improved. However, since device structures became smaller, circuit aging due to operational and environmental conditions can be accelerated. Circuit aging causes a performance degradation and eventually a system error. In reliable systems, a failure due to aging might cause a great disaster. Therefore, these systems need a performance degradation prediction function so that they can take action in advance before a failure occurs. This paper presents an on-line circuit performance degradation monitoring scheme for predicting a failure by detecting performance degradation during circuit normal operation. In our proposed scheme, IEEE 1149.1 output boundary scan cells and TAP controller are reused. The experimental result shows that the proposed architecture can monitor the performance degradation during normal operation without stopping the circuit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.39-42
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• 2018

In this paper, a low-power MPPT interface circuit for vibration energy harvesting sources is presented. The designed circuit rectifies the harvested ac type energy to the dc type energy required to drive the system, and periodically samples and holds the open circuit voltage (Voc) through the MPPT controller, and transfers the harvested power to the load while maintaining the input voltage at 1/2 of the maximum available power point. All circuits have been designed using a 0.35-um CMOS technology, and the operation has been verified through simulation. Simulation results show that the designed circuit consumes 98nA of current at 3V input voltage and the maximum power efficiency is 99.21%. The designed chip occupies $1.281mm{\times}1.236mm$.

• Journal of IKEEE
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• v.16 no.4
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• pp.322-327
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• 2012

In this paper, a digital phase-locked loop(Digital-PLL) circuit with a new phase-to-digital converter(P2D) is described. The proposed digital PLL is composed a P2D, a digital loop filter(DLF), and a digitally controlled oscillator(DCO). The P2D generates a digital code for a phase error. The proposed P2D used a binary phase frequency detector(BPFD) and a counter in place of a time-to-digital converter(TDC) for simple structure, compact area and low power consumption. The proposed circuit was designed with CMOS 0.18um process. The simulation shows the circuit operates with the 1.0 to 2.2GHz with the power consumption of 16.2mW at 1.65GHz and the circuit occupies the chip area of $0.096mm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.5 s.120
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• pp.539-546
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• 2007

In this paper, a 3-D EM simulation methodology for on-chip spiral inductor analysis has provided and it is shown that the methodology can be adapted to the highly predictable design for CMOS VCO. LC-resonator type VCO have fabricated by using standard 0.25 um CMOS process. And the LC VCO layout case which has pattern ground shielded inductors and the other layout case which has no pattern grounded inductors were fabricated for the verification of their effects on the VCO's phase noise by reducing the Q-factor of inductors. Fabricated VCO has 3.094 GHz, -12.15 dBm output at the tuning voltage of 2.5 V, and from the simulation, Q-factor of the pattern grounded inductor has increased 8% at 3 GHz, and from the measurement results, the phase noise has reduced by 9 dB at the 3 MHz off-set frequency for the pattern grounded inductor layout case.

• Journal of Advanced Navigation Technology
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• v.17 no.5
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• pp.560-567
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• 2013

In this paper, it is proposed the fault detection method of the ASIC, without the Test Requirement Document(TRD), extracting internal logic circuit and analyzed the function of the ASIC using the multipurpose development program and simulation. If there don't have the TRD, it is impossible to analyze the operation of the circuit and find out the fault detection in any chip. Therefore, we make the TRD based on the analyzed logic data of the ASIC, and diagnose of the ASIC circuit at the gate level through the signal control of I/O pins using the Dynamic Pattern signal. According to the experimental results of the proposed method, we is confirmed the good performance of the fault detection capabilities which applied to the non-memory circuit.

• Journal of Convergence for Information Technology
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• v.11 no.9
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• pp.124-129
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• 2021

A time-interpolation technique has been applied to the conventional FLASH analog-to-digital converter (ADC) to increase a number of quantization level, thus it reduces not only a power dissipation, but also minimize an active chip area. In this work, we demonstrated 5-bit ADC which has 31 quantization levels consisting of 16 conventional voltage-mode comparators and 15 time-mode comparators. As a result, we have achieved about 48.4% voltage-mode comparator reductions. The ADC is fabricated in a 14nm fin Field-effect transistor (FinFET) process with an active die area of 0.0024 mm2 while consuming 0.82 mW through a 0.8 V supply. At 400-MS/s conversion rate, the ADC performs 28.03 dB SNDR (4.36 ENOB) at 21MHz input frequency.