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VLSI Design of H.263 Video Codec Based on Modular Architecture  

Kim, Myung-Jin (ImpressTek, Co., Ltd.)
Lee, Sang-Hee (ImpressTek, Co., Ltd.)
Kim, Keun-Bae (ImpressTek, Co., Ltd.)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SP / v.39, no.5, 2002 , pp. 477-485 More about this Journal
Abstract
In this paper, we present an efficient hardware architecture for the H.263 video codec and its VLSI implementation. This architecture is based on the unified interface by which internal hardware engines and an internal RISC processor are connected one another. The unified interface enables the modular design of internal blocks, efficient hardware/software partitioning, and pipelined paralled operations. The developed VLSI supports the H.263 version 2 profile 3 @ level 10, and moreover, both the control protocol H.245 and the multiplexing protocol H.223. Therefore, it can be used for the complete ITU-T H.324 or 3GPP 3G 324M multimedia processor with the help of an external audio codec. Simultaneous encoding and decoding of QCIF format images at a rate greater than 15 frames per second is achieved at 40 MHz clock frequency.
Keywords
H.263; Video Codec; VLSI;
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