• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4A
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• pp.408-416
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• 2010

A dumbbell-type CPW transmission-line structure has been proposed to improve the return loss of the transmission line between a driver IC and flip-chip-bonding VCSEL(Vertical Cavity Surface Emitting Laser) in a hybrid opto-electric circuit board(OECB). The proposed structure used a pair of dummy ground solder balls on the ground lines for flip-chip bonding of the VCSEL and designed the dumbbell-type CPW transmission line to improve reflection characteristics. The simulated results revealed that the return loss of the dumbbell-type CPW transmission line was 13-dB lower than the conventional CPW transmission line. A 4-dB improvement in the return loss was obtained using the dummy ground solder balls on the ground lines. The variation rate of the reflection characteristic with the variation of terminal impedances of the transmission line (at the output terminal of the driver IC and the input terminal of the VCSEL) is about ${\pm}2.5\;dB$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.63-71
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• 2000

Infrared (IR) detector chip, which detects the IR radiation from all of the objects and converts to image signal, is usually fabricated using hybrid bonding technology with detector away and readout integrated circuit (ROIC). In this study, we designed the readout circuit and simulated its operations. Fabricating readout circuit chips, we measured operation results satisfying its design requirements in 6V supply voltage. After we mount the IR detector chip in the manufactured thermal image system, thermal images were implemented. The obtained thermal images for high and room temperature target objects are sufficiently recognizable. Using the low noise thermal Image system, we expect to obtain thermal images with higher temperature resolution.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.3
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• pp.53-58
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• 2008

In this study, we fabricated embedded IC (Double Pole Double throw switch chip) polymer substrate and evaluate it for 2.4 GHz WiFi application. The switch chips were laminated using FR4 and ABF(Ajinomoto build up film) as dielectric layer. The embedded DPDT chip substrate were interconnected by laser via and Cu pattern plating process. DSC(Differenntial Scanning Calorimetry) analysis and SEM image was employed to calculate the amount of curing and examine surface roughness for optimization of chip embedding process. ABF showed maximum peel strength with Cu layer when the procuring was $80\sim90%$ completed and DPDT chip was laminated in a polymer substrate without void. An embedded chip substrate and wire-bonded chip on substrate were designed and fabricated. The characteristics of two modules were measured by s-parameters (S11; return loss and S21; insertion loss). Insertion loss is less than 0.55 dB in two presented embedded chip board and wire-bonded chip board. Return loss of an embedded chip board is better than 25 dB up to 6 GHz frequency range, whereas return loss of wire-bonding chip board is worse than 20 dB above 2.4 GHz frequency.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.65-70
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• 2014

Warpage of top packages to form thin package-on-packages was measured with progress of their process steps such as PCB substrate itself, chip bonding, and epoxy molding. The $100{\mu}m$-thick PCB substrate exhibited a warpage of $136{\sim}214{\mu}m$. The specimen formed by mounting a $40{\mu}m$-thick Si chip to such a PCB using a die attach film exhibited the warpage of $89{\sim}194{\mu}m$, which was similar to that of the PCB itself. On the other hand, the specimen fabricated by flip chip bonding of a $40{\mu}m$-thick chip to such a PCB possessed the warpage of $-199{\sim}691{\mu}m$, which was significantly different from the warpage of the PCB. After epoxy molding, the specimens processed by die attach bonding and flip chip bonding exhibited warpages of $-79{\sim}202{\mu}m$ and $-117{\sim}159{\mu}m$, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.67-73
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• 2009

Compared to the chip-bonding process utilizing solder bumps, flip chip process using Cu pillar bumps can accomplish fine-pitch interconnection without compromising stand-off height. Cu pillar bump technology is one of the most promising chip-mounting process for RF packages where large gap between a chip and a substrate is required in order to suppress the parasitic capacitance. In this study, Cu pillar bumps and Sn bumps were electroplated on a chip and a substrate, respectively, and were flip-chip bonded together. Contact resistance and chip shear force of the Cu pillar bump joints were measured with variation of the electroplated Sn-bump height. With increasing the Sn-bump height from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance was improved from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$ and the chip shear force increased from 3.8 N to 6.8 N. On the contrary, the aspect ratio of the Cu pillar bump joint decreased from 1.3 to 0.9. Based on the variation behaviors of the contact resistance, the chip shear force, and the aspect ratio, the optimum height of the electroplated Sn bump could be thought as 20 ${\mu}m$.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.3
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• pp.39-44
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• 2015

We investigated the effect of CNT-Ag composite pad on the contact resistance of flip-chip joints, which were formed by flip-chip bonding of Cu/Au chip bumps to Cu substrate metallization using anisotropic conductive adhesive. Lower contact resistances were obtained for the flip-chip joints which contained the CNT-Ag composite pad than the joints without the CNT-Ag composite pad. While the flip-chip joints with the CNT-Ag composite pad exhibited average contact resistances of $164m{\Omega}$, $141m{\Omega}$, and $132m{\Omega}$ at bonding pressures of 25 MPa, 50 MPa, and 100 MPa, the flip-chip joints without the CNT-Ag composite pad had an average contact resistance of $200m{\Omega}$, $150m{\Omega}$, and $140m{\Omega}$ at each bonding pressure.

• Journal of Advanced Marine Engineering and Technology
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• v.37 no.4
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• pp.351-357
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• 2013

In flip chip packaging, underfill process is used to fill epoxy bonder into the gap between a chip and a substrate in order to improve the reliability of electronic devices. Underfill process by capillary motion can give rise to unwanted air void formations since the arrangement of solder bumps affects the interfacial dynamics of flow meniscus. In this paper, the unsteady flows in the capillary underfill process are visualized and then the racing effect and merging of the meniscus are investigated according to the arrangement of solder bumps. The result is shown that at higher bump density, the fluid flow perpendicular to the main direction of flow becomes stronger so that more air voids are formed. This phenomenon is more conspicuous at a staggered bump array than at a rectangular bump array.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.69-73
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• 2008

This article shows that the susceptibility of the device pattern to thermal stress-induced damage has a strong dependence on its proximity to the device comer in semiconductor devices utilizing lead-on-chip (LOC) die attach technique. The result, as explained based on numerical calculation and experiment, indicateds that the stress-driven damage potential of the passivation layer is the highest at the device comer. Thus, the bonding pads, which are very susceptible to passivation damage, should be designed to be located along the central region rather than the peripheral region of the device.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2017.11a
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• pp.144-145
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• 2017

최근 전자 기기의 크기가 줄어들고 PCB의 사이즈와 반도체 패키지의 크기가 소형화되어 플립 칩 본딩(Flip chip bonding) 기술을 적용한 반도체 패키지 방식이 점점 늘어나고 있다. 이에 따라 PCB와 반도체 칩 사이를 연결하기 위해 응용되던 BGA(Ball Grid Array)에 핀 배열 대신 사용되는 범프(Bump)를 50um 이내의 초미세 범프로 만들어 일정한 배열을 유지하는 것이 중요하다. 또한 초미세 범프의 모양과 품질이 패키지 수율과 밀접하게 연관되기 때문에 이를 검사할 수 있는 기술이 필수적이다. 이에 본 논문은 초미세 범프측정을 할 수 있는 시스템 개발을 위한 측정 대상의 특징과 사용할 수 있는 광학계를 분석하였고, 획득된 영상을 가지고 딥러닝을 적용하여 정확하게 불량여부를 판별할 수 있는 초미세 범프 측정 시스템을 고안하였다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.2
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• pp.1364-1369
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• 2015

As the wire bonding process has been converted into BUMP process due to the high density integration of semiconductor chip, the telecommunication line connecting to semiconductor chip and external devices have become finer. As a result, a more precise work is necessary. However, it is difficult to control quantity given the nature of high viscosity of PSPI and the yield rate continues to decline due to the inflow of bubble. Therefore, this paper developed the D&P(degassing and pumping) system to remove and supply gas that is generated from coating the high viscosity photosensitive polyimide(PSPI) in the semiconductor BUMP process.