• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1C
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• pp.18-24
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• 2005

In this paper, a new trellis-coded differential unitary space-time modulation (TC-DUSTM) scheme based on amplitude/phase-shift-keying (APSK) signals is proposed. In particular, the design criterion of the trellis coding is proposed to combine the trellis coding and DUSTM scheme based on APSK constellation. From the computer simulations, we verify the superiority of the proposed TC-DUSTM based on APSK signals at the higher transmission rate. In addition, the proposed scheme can suppress the irreducible error of the differential scheme.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.5
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• pp.565-570
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• 2015

Spread spectrum communications have increased interest due to their immunity to channel fading and low probability of intercept. One of the limitations of the traditional digital spread spectrum systems is the need for spreading code synchronization. Chaotic communication is the analogue alternative of digital spread spectrum systems beside some extra features like simple transceiver structures. In this paper, This paper was used instead of the digital modulation and demodulation carriers for use in the chaotic signal in a digital communication system among the chaotic modulation schemes, the Differential Chaos Shift Keying(DCSK) is the most efficient one because its demodulator detects the data without the need to chaotic signal phase recovery. Also Implementation of Differential Chaos Shift Keying Communication System Using Matlab/Simulink and the receiver con decode the binary information sent by the transmitter, performance curves of DCSK are given in terms of bit-error probability versus signal to noise ratio with spreading factor as a parameter and we compare it to BPSK modulation.

• Journal of Satellite, Information and Communications
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• v.9 no.1
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• pp.13-16
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• 2014

In applying LCD to TV application, one of the most significant factors to be improved is image sticking on the moving picture. LCD is different from CRT in the sense that it's continuous passive device, which holds images in entire frame period, while impulse type device generate image in very short time. To reduce image sticking problem related to hold type display mode, we made an experiment to drive TN-LCD like CRT. We made articulate images by fast refreshing images, and we realized the ratio of refresh time by counting between on time and off time for video signal input during 1 frame (16.7ms). Conventional driving signal cannot follow fast on-off speed, so we evaluated new signal generator using SDI (Serial Data Interface) mode signal generator. We realized articulate image generation similar to CRT by high fast full HD (High Definition) signals and TN-LCD overdriving. As a result, reduced image sticking phenomenon was validated by naked eye and response time measurement.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.3
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• pp.453-460
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• 2019

The SR-DCSK(Short Reference Differential Chaos Shift Keying) is a variant of DCSK that improves data transmission speed and energy efficiency without additional complexity. However, even when the reference signal of the optimum length is applied, the BER performance of the SR-DCSK is not better than that of the conventional DCSK. In this paper, we propose a scheme to improve the performance of SR-DCSK by applying two scale factors (scale coefficients) to the reference signal and the information signal, respectively. And the performance of the proposed method is analyzed by BER using Gaussian Approximation. Based on the derived BER expressions, we minimize the BER for a given system parameter to optimize the ratio of the two coefficients. Simulation results confirm that the BER of the proposed method is much improved over the SR-DCSK when we apply the optimal ratio of the two scale factors.

• Journal of the Korean Institute of Telematics and Electronics
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• v.9 no.4
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• pp.17-24
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• 1972

A simply constructed and inexpensive amplifier that exhibits unusually low noise is studied. The high-performance differential amplifier combines high input impedence, adjustable gain, low in put noise and low output impedance. The amplifier is particularly useful in applications which call for large amplificaions of very low level signals.

• Journal of Biomedical Engineering Research
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• v.21 no.5
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• pp.477-485
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• 2000

본 논문에서는 신경신호기록을 위한 반도체 미세전극용 전치증폭기의 잡음특성을 설계하기 위한 체계적인 방법을 제시한다. 세포외기록(extracellular recording)에 의하여 측정된 신경신호와 전형적인 CMOS소자의 저주파 잡음특성을 함계 고려하여 전체 신호대잡음비를 계산하였다. 2단 CMOS 차동증폭기에 대한 해석과 함께 신호대잡음비에 중요한 영향을 끼치는 요소들에 대하여 설명하였다. 출력잡음전력에 대한 해석적인식을 유도하였으며 이로부터 회로설계자가 조절할 수 있는 주파수응답과 소자 파라미터들을 결정하였다. 입력소자의 크기와 트랜스컨덕턴스의 비가 최적영역으로부터 약간 벗어날 경우에 신호대잡음비가 크게 저하됨을 보였다. 이와 함께 만족스런 잡음특성을 위한 증폭이의 설계 변수 값들도 제시하였다.

• Journal of IKEEE
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• v.14 no.1
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• pp.8-16
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• 2010

This paper presents a design of the successive approximation ADC(SA-ADC) applicable to a midium-low speed analog-front end(AFE) for the maximum 15MS/s CCD image processing. SA-ADC is effective in applications ranging widely between low and mid data rates due to the large power scaling effect on the operating frequency variations in some other way of pipelined ADCs. The proposed design exhibits some distinctive features. The "differential capacitor-coupling scheme" segregates the input sampling behavior from the sub-DAC incorporating the differential input and the sub-DAC output, which prominently reduces the loading throughout the signal path. Determining the MSB(sign bit) from the held input data in advance of the data conversion period, a kind of the signed successive approximation, leads to the reduction of the sub-DAC hardware overhead by 1 bit and the conversion period by 1 cycle. Characterizing the proposed design in a 3.3 V $0.35-{\mu}m$ CMOS process by Spectre simulations verified its validity of the application to CCD analog front-ends.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.291-297
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• 2011

In this paper, the differential quantized method and the parallel method to reduce the size of ROM in the direct digital frequency synthesizer(DDFS) is proposed And we design the DDFS by FPGA The new ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine is saved by the quantized-ROM(Q-ROM) and the differential ROM(D-ROM). Also we design the phase-to-sine converter using the phase accumulator of parallel type for generating the high frequency. So the total size of the ROM in the proposed DDFS is significantly reduced compared to the original ROM The ROM compression ratio of 67.5% is achieved by this method. Also, the power consumption is decreased according to the ROM size reduction and we can design the DDFS generating the high frequency.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.192-198
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• 2007

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer(DDFS) is proposed. The new ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine is stored by the quantized-ROM(Q-ROM) and the differential ROM(D-ROM). To reduce the ROM size, we use the differential quantization technique with this two ROM. First, we quantize the quarter sine wave with the $2^L$ address and store the quantized value at the Q-ROM. Second, after the $2^L$ address are equally divided into $2^M$ sampling intervals, the sampling value is quantized. And the D-ROM store only the difference between this quantized value and the Q-ROM. So the total size of the ROM in the proposed DDFS is significantly reduced compared to the original ROM. The ROM compression ratio of 67.5% is achieved by this method. Also, the power consumption is affected mostly by this ROM reduction.

• Journal of Navigation and Port Research
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• v.26 no.5
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• pp.525-528
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• 2002

The proposed EMC filter composed with feed-through capacitors and ferrite beads of high permeability was prepared which satisfy the EMC standard for a wide-band noise signal in the frequence of 10 MHz to 1.5 GHz in power supply line. The optimum structure of ferrite bead was found by calculating the load effect of ferrite beads. As a result, the filter showed excellent differential- and common-mode noises filtering characteristics above 30dB in the frequency band from 10 MHz to 1.5 GHz. The immunity characteristics are improved more than 10 to 30 dB over the frequency band from DC to 1.8GHz.