• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.41-48
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• 2005

The crosstalk effects that can be observed in the very dee submicron semiconductor chips are due to the coupling capacitances between interconnect lines. The accuracy of the full-chip timing analysis is determined by the accuracy of the estimated propagation delays of cells and interconnects within the chip. This paper presents a CMOS cell driver model and delay calculation algerian capturing the crosstalk effects due to the coupling capacitances. The proposed model and algorithm were implemented in a delay calculation program and used to estimate the propagation delays of the benchmark circuits extracted from a chip layout. We observed that the average discrepancy from HSPICE simulation results is within $1\%$ for the circuits with a victim affected by $0\~10$ aggressors.

• The Transactions of the Korea Information Processing Society
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• v.6 no.8
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• pp.2204-2212
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• 1999

In this paper, we present techniques which perform incremental timing analysis using Timed Boolean Algebra that solves the false path problem and extracts the timing information in combinational circuits. Our algorithm sets histories of internal inputs that are substituted for internal output and extracts maximal delays through checking sensitizability of primary outputs. Once finding the sum of primitive delay terms, then it applies modified delay with referencing histories of primary output and it can extract maximal delays of primary outputs fast and efficiently. When the structure of circuit is changed, there is no need to compute the whole circuit again. We can process partial timing analysis of computing on the gates that are need to compute again. These incremental timing analysis methods are considered both delay changes and structure of circuit, and can reduce the costs of a trial error in the circuit design.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.5
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• pp.241-249
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• 2003

Carry lookahead(CLA) circuitry of decimal adders is proposed aiming at delay reduction. The truncation error in calculation of monetary interests may accumulate yielding a substantial amount of errors. Binary Coded Decimal(BCD) additions. for example, eliminate the truncation error in a fractional representation of decimal numbers. The proposed BCD carry lookahead scheme is aiming at the speed improvements without any truncation errors in the addition of decimal fractions. The delay estimation of the BCD CLA is demonstrated with improved performance in addition. Further reduction in delay can be achieved introducing non-weighted number system such as the excess-3 code.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.6
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• pp.354-360
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• 2002

Delay estimation must be simple and efficient, since millions or more delay calculations may be required during a timing-driven placement stage. We have developed a new Modified Elmore delay estimation method, which is significantly more accurate than the original Elmore delay by considering resistance shielding effects, but has the same order of complexity with that of Elmore delay. Experimental results show that the suggested technique can significantly reduce the error in estimated delay, from 31.6 ~ 145.2% to 2.5 ~ 22.7%.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.1-9
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• 1999

Timing-level circuit analyses are used to obtain fast and accurate results, and the analysis of gate and interconnect delay is necessary to validate the correctness of circuit design. This paper proposes an efficient algorithm which simultaneously calculates the gate delay and the transition time of linearized voltage source for subsequent interconnect delay calculation. The notion of effective capacitance is used to calculate the gate delay and the transition time of linearized voltage source which considers the on-resistance of driving gate. The procedure for obtaining the gate delay and the transition time of linearized voltage source has been developed through an iterative operation using the precharacterized data of gates. While previous methods require extra information for the transition time calculation of linearized voltage sources, our method uses the derived data during the gate delay calculation process, which does not require any change in the precharacterization process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10C
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• pp.1370-1377
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• 2004

Optimal control gain for time-delay systems is made by an optimal control gain for delay-free systems multiplied by a state transition function for the delay time. The optimal control gain for delay-free systems is obtained by pushing two zeros of the PID controller closely to a larger pole of the second order plant. Thus the optimal tuning of PID controller for time-delay second order system is able to be obtained by calculation for the state transition function.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1997.11a
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• pp.9-13
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• 1997

본 논문에서는 two-ray 시간선택성 레일레이 페이딩 채널상에서 DPSK 신호를 차동검출 (differential detection)할 때 심볼에러율을 분석한다. 현재까지 수행된 많은 연구는 주파수 선택성 페이딩 채널 및 단일 경로 시간선택성 페이딩 채널을 대상으로 하였고, 다경로 시간선택성 페이딩 채널을 대상으로 한 예는 극히 드물다. 또한 다경로 시간선택성 페이딩 채널을 가장 간단히 모델링 할 수 있는 two-ray 페이딩 채널에 대한 연구도 지금까지 수행된 예가 극히 적다. 본 논문에서는 심볼열의 형태에 따라 수신신호들간의 관계를 세가지 그룹으로 나눈 후 각각의 경우에 대하여 위상 옵셋값을 계산하는 방식을 취하였다. 이와 같이 계산된 위상옵셋과 신호대 잡음비를 인자로 하여 차동검출된 신호가 가지는 위상의 확률밀도 함수를 계산하고 이 함수를 이용하여 심볼에러율을 계산하였다. 결과로부터 two-ray 페이딩 채널의 특성을 결정짓는 지연시간과 지연신호의 전력이 증가함에 따라 위상 옵셋값 및 에러율이 모두 증가하는 것을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.83-88
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• 2008

In this paper, a new scheduling method considering bit-level delays for high-level synthesis is proposed. Conventional bit-level delay calculation for high-level synthesis was usually limited for specific resources. However, we have developed an efficient bit-level delay calculation method which is applicable to various resources, in this research. This method is applied to scheduling. The scheduling algorithm is based on list scheduling and executes chaining considering bit-level delays. Furthermore, multi-cycle chaining can be allowed to improve performance under resource constraints. Experimental results on several well-known DSP examples show that our method improves the performance of the results by 14.7% on the average.

• Proceedings of the Korean Information Science Society Conference
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• 2011.06d
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• pp.283-286
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• 2011

무선 멀티홉 네트워크에서 멀티미디어 트래픽의 QoS(Quality of Service) 지원을 위하여 EDCA(Enhanced Distributed Channel Access) 기반의 동적 우선순위 할당 기법이 다수 제안되었다. 해당 기법들은 각 홉에서의 최소한의 전송 지연 보장을 위하여 클래스별 예상 지연 시간을 계산한다. 하지만 각 클래스별 예상 지연 시간의 계산은 무선 채널에서의 간섭, 충돌 및 링크 품질에 영향을 받기 때문에 정확한 예측이 어렵다. 본 논문에서는 EDCA 기반의 동적 우선순위 할당을 위한 정교한 클래스별 지연 시간 예측 기법을 제안한다. 제안하는 기법은 무선 채널의 링크 품질과 전송 패킷의 크기를 고려하여 좀더 실제와 유사한 지연 시간을 예측할 수 있다. 실험을 통해 제안하는 기법이 기존의 기법보다 정확성이 높으며 이를 통해 동적 우선순위 할당 기법의 성능을 향상시킬 수 있음을 확인하였다.

• Journal of the Korean Chemical Society
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• v.44 no.4
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• pp.328-336
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• 2000

The pulsed-delayed extraction (PDE) in linear time-of-flight mass spectrometer(TOF MS) is characterized on the enhancement of resolution, mass-depth of focus and effect of instrumentahan 2000. The ion signals separate isotopically by up to molecular weight of 2500 in instrumental broadening of 5 ns, which is a good agreement with calculation. The fragmentation paths of PPG can be sug-gested by the isotopica distributions of fragment series produced when PPG desorbed from graphite surface.