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A CMOS Cell Driver Model to Capture the Effects of Coupling Capacitances  

Cho, Kyeong-Soon (Department of Electronics and Information Engineering, Hankuk University of Foreign Studies)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.11, 2005 , pp. 41-48 More about this Journal
Abstract
The crosstalk effects that can be observed in the very dee submicron semiconductor chips are due to the coupling capacitances between interconnect lines. The accuracy of the full-chip timing analysis is determined by the accuracy of the estimated propagation delays of cells and interconnects within the chip. This paper presents a CMOS cell driver model and delay calculation algerian capturing the crosstalk effects due to the coupling capacitances. The proposed model and algorithm were implemented in a delay calculation program and used to estimate the propagation delays of the benchmark circuits extracted from a chip layout. We observed that the average discrepancy from HSPICE simulation results is within $1\%$ for the circuits with a victim affected by $0\~10$ aggressors.
Keywords
Crosstalk;
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Times Cited By KSCI : 1  (Citation Analysis)
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