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Scheduling Considering Bit-Level Delays for High-Level Synthesis  

Kim, Ji-Woong (Mechatronics Engineering, Hanyang University)
Shin, Hyun-Chul (Electric Engineering and Computer Science, Hanyang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.11, 2008 , pp. 83-88 More about this Journal
Abstract
In this paper, a new scheduling method considering bit-level delays for high-level synthesis is proposed. Conventional bit-level delay calculation for high-level synthesis was usually limited for specific resources. However, we have developed an efficient bit-level delay calculation method which is applicable to various resources, in this research. This method is applied to scheduling. The scheduling algorithm is based on list scheduling and executes chaining considering bit-level delays. Furthermore, multi-cycle chaining can be allowed to improve performance under resource constraints. Experimental results on several well-known DSP examples show that our method improves the performance of the results by 14.7% on the average.
Keywords
chaining;
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