• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.23 no.3
• /
• pp.361-366
• /
• 2012

This paper proposes a low power capacitor cross-coupled 5.2 GHz band low noise amplifier(LNA) using the current-reused topology with the TSMC 0.18 ${\mu}m$ CMOS process. The proposed 5.2 GHz band LNA uses a capacitor cross-coupled $g_m$-boosting method for reducing current flow of circuit and a current-reused topology to decrease total power dissipation. The parallel LC networks are used to reduce size of spiral inductors. The simulation results show high gain of 17.4 dB and noise figure(NF) of 2.7 dB for 5.2 GHz.

• Journal of Satellite, Information and Communications
• /
• v.5 no.2
• /
• pp.82-86
• /
• 2010

In this paper, a power amplifier module for WCDMA base-station applications is designed and implemented using GaN field-effect transistors (FETs), which uses an envelope tracking bias system. The designed module consists of an high gain MMIC amplifier, a driver amplifier, a power amplifier, and bias circuits for envelope tracking applications. Especially, a FET bias sequencing circuit and two isolators are integrated for stable RF operations. All circuits are assembled within a single housing, so its dimension is just $17.8{\times}9.8{\times}2.0\;cm3$. Measured results show that the developed power amplifier module has good envelope tracking capability: the power-added efficiency of 35% at the output power range from 30dBm to 40dBm over a wide range of drain bias.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.3 no.2
• /
• pp.339-346
• /
• 1999

A RF receiver section for INMARSAT-C external mounting unit was designed, fabricated and evaluated. Using a INA-03184, the high gain amplifier consists of matched amplifier type. Active bias circuitry can be used to provide temperature stability without requiring the large voltage drop or relatively high-dissipated power needed with a bias stabilization resistor. The bandpass filter was used to reduce a spurious level. As a result, the characteristics of the receiver section implemented here show 60 dB in gain, 44.83 dBc in a spurious level. The voltage standing wave ratios(VSWR)of input output port are less than 1.8:1, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.43 no.3 s.345
• /
• pp.68-77
• /
• 2006

This paper presents a new Design-for-Testability (DfT) circuit for 4.5-5.5GHz low noise amplifiers (LNAs). The DfT circuit measures gain, noise figure, input impedance, input return loss, and output signal-to-noise ratio for the LNA without external expensive equipment. The DfT circuit is designed using 0.18m SiGe technology. The circuit utilizes input impedance matching and DC output voltage measurements. The technique is simple and inexpensive.

• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.8 no.3
• /
• pp.83-90
• /
• 2009

This paper presents the design and measurement of a flight model for a Ku-Band Linearized Channel Amplifier. All MMICs, Variable Gain Amplifier (VGA), Variable Voltage Attenuator ('.IVA), Branch line Coupler and Detector for Pre-distorter are fabricated using a Thin-Film Hybrid process. The performance of the fabricated module is verified through the radio frequency circuit simulation tool and electrical function test in space environment.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.12 no.1
• /
• pp.65-70
• /
• 2001

This paper presents a Receiver MMIC for the CDMA terminal. The complete circuit is composed of Low Noise Amplifier, Down Conversion Mixer, Intermediate Frequency Amplifier and Bias circuit. The Bias circuit implementation, which allows for compensation for threshold voltage and power supply voltage variation are provided. The proposed topology has high linearity and low noise characteristics. Results of the designed circuit are as follows: Overall conversion gain is 28.5 dB, input IP3 of LNA is 8 dBm, input IP3 of down conversion mixer is 0 dBm and total DC current consumption is 22.1 mA.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.11
• /
• pp.130-137
• /
• 2013

This paper presents analog front-end(AFE) circuits for bio-potential measurement. The proposed AFE is composed of IA(instrument amplifier), BPF(band-pass filter), VGA(variable gain amplifier) and SAR(successive approximation register) type ADC. The low gm(LGM) circuits with current division technique and Miller capacitance with high gain amplifier enable IA to implement on-chip AC-coupling without external passive components. Spilt capacitor array with capacitor division technique and asynchronous control make the 12-b ADC with low power consumption and small die area. The total current consumption of proposed AFE is 6.3uA at 1.8V.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.12
• /
• pp.82-90
• /
• 2011

A novel class AB current subtracter(CS) and its application to Norton amplifier(NA) for low-power current-mode signal processing are designed. The CS is composed of a translinear cell, two current mirrors, and two common-emitter(CB) amplifiers. The principle of the current subtraction is that the difference of two input current applied translinear cell get from the current mirror, and then the current amplify through CB amplifier with ${\beta}$ times. The NA is consisted of the CS and wideband voltage buffer. The simulation results show that the CS has current input impedance of $20{\Omega}$, current gain of 50, and current input range of $i_{IN1}$ > $i_{IN2}{\geq}4I_B$. The NA has unit gain frequency of 312 MHz, transresistance of 130 dB, and power dissipation of 4mW at ${\pm}2.5V$ supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.20 no.3
• /
• pp.264-272
• /
• 2009

In this paper, a Ka-band 10 W power amplifier module is designed and fabricated using MIC(Microwave Integrated Circuit) module technology which combines multiple power MMIC(Monolithic Microwave Integrated Circuit) chips on a thin film substrate. Modified Wilkinson power dividers/combiners are used for millimeter wave modules and CBFGC-PW-Microstrip transitions are utilized for reducing connection loss and suppressing resonance in the high-gain and high-power modules. The power amplifier module consists of seven MMIC chips and operates in a pulsed mode. for the pulsed mode operation, a gate pulse control circuit supplying the control voltage pulses to MMIC chips is designed and applied. The fabricated power amplifier module shows a power gain of about 58 dB and a saturated output power of 39.6 dBm at a center frequency of the interested frequency band.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.8
• /
• pp.22-26
• /
• 2012

This paper introduces a 2.5-Gb/s optical receiver implemented in a standard 1P4M 0.18um CMOS technology for the applications of active optical HDMI cables. The optical receiver consists of a differential transimpedance amplifier(TIA), a five-stage differential limiting amplifier(LA), and an output buffer. The TIA exploits the inverter input configuration with a resistive feedback for low noise and power consumption. It is cascaded by an additional differential amplifier and a DC-balanced buffer to facilitate the following LA design. The LA consists of five gain cells, an output buffer, and an offset cancellation circuit. The proposed optical receiver demonstrates $91dB{\Omega}$ transimpedance gain, 1.55 GHz bandwidth even with the large photodiode capacitance of 320 fF, 16 pA/sqrt(Hz) average noise current spectral density within the bandwidth (corresponding to the optical sensitivity of -21.6 dBm for $10^{-12}$ BER), and 40 mW power dissipation from a single 1.8-V supply. Test chips occupy the area of $1.35{\times}2.46mm^2$ including pads. The optically measured eye-diagrams confirms wide and clear eye-openings for 2.5-Gb/s operations.