• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.386-387
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• 2011

본 논문은 플라즈마 방전장치 구동을 위한 가변 전압/주파수 전원장치를 제안한다. 제안하는 전원장치는 가변전압을 위한 벅-부스트 컨버터와 주파수 변환을 위한 푸쉬-풀 인버터로 구성된다. 제안하는 전원장치의 벅-부스트 컨버터는 계통전류 고조파 저감과 DC링크 캐패시터 최소화를 위하여 PFC(Power Factor Collection)기법을 적용한다. 그리고 푸쉬-풀 인버터는 출력 변압기의 자기포화를 막기 위해 전류제한기법을 추가한다. 또한 불분명한 부하와 출력 트랜스의 공진 상황에서 전압 안정화를 위해 출력전압을 피드백하여 제어한다. 본 논문은 1[kW]급 플라즈마 전원장치를 통하여 제안하는 토폴로지와 제어방법의 타당성을 검증한다.

• Journal of IKEEE
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• v.16 no.3
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• pp.203-210
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• 2012

Since the non-overlapping gate driver used in conventional DC-DC boost converters generates fixed dead-times, the converters suffer from the body-diode conduction loss or the charge-sharing loss. To reduce the efficiency degradation due to these losses, this paper presents a PWM DC-DC boost converter with adaptive dead-time control. The proposed DC-DC boost converter delivering 3.3V output from a 2.5V input is designed with CMOS $0.3{\mu}m$ technology. It operates at 500kHz and has a maximum power efficiency of 97.3%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.5
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• pp.1155-1161
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• 2014

This paper proposes a start-up voltage generator for reducing the minimum input supply voltage of DC-DC boost converters to 250mV. The proposed start-up voltage generator boosts 250mV input voltage to over 500mV to charge the capacitor for starting the boost converter. After the boost converter operates initially with the supply voltage charged in the capacitor, it uses its boosted output voltage for the supply voltage. Therefore, after the start-up operation, the proposed DC-DC boost converter works as the same as the conventional one. The proposed start-up voltage generator reduces the threshold voltage of the transistors by adjusting the body voltage at a low input voltage. This causes the higher clock frequency and the larger current to a Dickson charge-pump for boosting the input voltage. The proposed start-up voltage generator was implemented with a $0.18{\mu}m$ CMOS process. Its clock frequency and output voltage were 34.5kHz and 522mV at 250mV input voltage, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.9
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• pp.2081-2086
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• 2015

The temperature sensor using ring oscillator is designed by 0.18㎛ CMOS process and the supply voltage is 1.5volts. The temperature sensor is designed by using temperature-independent and temperature-dependent ring oscillators and the output frequency of temperature-independent ring oscillator is constant with temperature and the output frequency of temperature-dependent ring oscillator decreases with increasing temperature. To convert the temperature to a digital value the output signal of temperature-independent ring oscillator is used for the clock signal and the output signal of temperature-dependent ring oscillator is used for the enable signal of counter. From HSPICE simulation results, the temperature error is less than form -0.7℃ to 1.0℃ when the operating temperature is varied from -20℃ to 70℃.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.151-158
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• 2002

In this paper, Phase locked microwave oscillator having the low phase noise and high stability for digital MMDS down converter was designed. we have been analyzed the low phase noise properties by the active device nonlinear equivalent circuits and derived the necessary and sufficient conditions for high stable voltage control oscillator. And it is applied to phase locked loop, we design the phase locked microwave oscillator of frequency synthesizer. Experimental results of designed phase locked oscillator shows -85dBc/Hz @ 10KHz phase noise properties and simulation result is -90Bc/Hz @ 10kHz respectively we shows that proposed low phase noise and stable conditions of phase locked microwave oscillator can be applied to design the high stable digital MMDS frequency synthesizer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.69-75
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• 2004

This work proposes an 8b 220 MS/s 230 mW 3-stage pipeline CMOS ADC with on-chip filers for temperature- and power- insensitive voltage references. The proposed RC low-pass filters improve switching noise performance and reduce reference settling time at heavy R & C loads without conventional off-chip large bypass capacitors. The prototype ABC fabricated in a 0.25 um CMOS occupies the active die area of 2.25 $\textrm{mm}^2$ and shows the measured DNL and INL of maximum 0.43 LSB and 0.82 LSB, respectively. The ADC maintains the SNDR of 43 dB and 41 dB up to the 110 MHz input at 200 MS/s and 220 MS/s, respectively, while the SNDR at the 500 MHz input is degraded as much as only 3 dB than the SNDR at the 110 MHz input.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.6
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• pp.533-539
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• 2015

In this paper, we designed a reconfigurable mixer for microwave broadband receiver. The proposed mixer using a anti-parallel diode is operated as a fundamental mixer or sub-harmonic mixer with respect to a control voltage. A fundamental mixer with a control voltage show a conversion loss of -10 dB, 1 dB compression point of 2.0 dBm at X-band/ Ku-band. On the other hand, it is performed as a sub-harmonic mixer with a conversion loss of -17 dB, 1 dB compression point of 2.0 dBm at Ka-band.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.31-40
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• 2009

This paper presents a design of a high performance DC-DC boost converter as a power module for SOC designs. It applied to this chip that reduced inductor and capacitor for integrating on a chip, and it operates with a switching frequency of 100MHz. It has reliability and stability in high switching frequency. The controller of DC-DC boost converter is designed by voltage-mode control method and compensated properly. The designed DC-DC converter is fabricated with the 0.18${\mu}m$ standard CMOS technology with a thick-gate oxide option. The overall die size is 8.14$mm^2$, and controller size is 1.15$mm^2$. The converter has the maximum efficiency over 76% for the output voltage of 4V and load current larger 300mA. The load regulation is 0.012% (0.5mV) for the load current change of 100mA.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.7
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• pp.649-656
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• 2002

This paper addresses the phase noise analysis of high-speed DH-PLL(Digital Hybrid Phase-Locked Loops) frequency synthesizer. Because of the additional quantization noise of D/A converter in DH-PLL, the phase noise of DH-PLL is increased than the conventional PLL. Three kinds of noise sources such as reference input, D/A converter, and VCO(Voltage Controlled Oscillator) are considered to analyze the phase noise. It largely depends on the closed loop bandwidth and frequency synthesis division ratio(N) so that we can decide the optimal closed loop bandwidth to minimize the phase noise of DH-PLL. It is shown that the simulation results closely match with the results of analytical approach.

• Journal of IKEEE
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• v.24 no.1
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• pp.319-325
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• 2020

In this paper, a discontinuous-conduction mode (DCM) DC-DC buck converter is presented for mobile device applications. The buck converter consists of compensator for stable operations, pulse-width modulation (PWM) logic, and power switches. In order to achieve small hardware form-factor, the number of off-chip components should be kept to be minimum, which can be realized with simple and efficient frequency compensation and digital soft start-up circuits. Burst-mode operation is included for preventing the efficiency from degrading under very light load condition. The DCM DC-DC buck converter is fabricated with 0.18-um BCDMOS process. Programmable output with external resistors is typically set to be 1.8V for the input voltage between 2.8 and 5.0V. With a switching frequency of 1MHz, measured maximum efficiency is 92.6% for a load current of 100mA.