• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.05a
• /
• pp.88-90
• /
• 2012

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a rail-to-rail input range. The proposed SAR ADC consists of a capacitor digital-analog converter (DAC), a SAR logic and a comparator. To reduce the frequency of an external clock, the internal clock which is asynchronously generated by the SAR logic and the comparator is used. The time-domain comparator with a offset calibration technique is used to achieve a high resolution. To reduce the power consumption and area, a split capacitor-based differential DAC is used. The designed asynchronous SAR ADC is fabricated by using a 0.18 um CMOS process, and the active area is $420{\times}140{\mu}m^2$. It consumes the power of 0.818 mW with a 1.8 V supply and the FoM is 91.8 fJ/conversion-step.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.12 no.2
• /
• pp.168-175
• /
• 1987

In this paper, a FFH-SS hybrid communication method using digital frequency synthesizer is proposed. This can simultaneously share the same frequency band with conventional band limited communication method without interference. In the experiment the selective hopping pattern is attained by some conbination of serial to parallel conversion of maximal code from pseudo random noise generater, and it is observed that the selective hopping band transition can be more easily achieved when the hop interval is nonuniform than it is uniform. Digital frequency synthesizer is now reported to have very poor spurious suppression ability below 50~60dB, the reason of this is observed from the experimental result, and the way of how to solve this problem is presneted.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.6 no.2
• /
• pp.151-158
• /
• 2002

In this paper, Phase locked microwave oscillator having the low phase noise and high stability for digital MMDS down converter was designed. we have been analyzed the low phase noise properties by the active device nonlinear equivalent circuits and derived the necessary and sufficient conditions for high stable voltage control oscillator. And it is applied to phase locked loop, we design the phase locked microwave oscillator of frequency synthesizer. Experimental results of designed phase locked oscillator shows -85dBc/Hz @ 10KHz phase noise properties and simulation result is -90Bc/Hz @ 10kHz respectively we shows that proposed low phase noise and stable conditions of phase locked microwave oscillator can be applied to design the high stable digital MMDS frequency synthesizer.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.2
• /
• pp.7-13
• /
• 2011

This paper presents a Time-to-Digital Converter which is a key block of an All-Digital Phase Locked Loop. In this work, a Vernier Delay Line is added in a conventional Gated Ring Oscillator, so it could get multi-phases and a high resolution. The Gated Ring Oscillator uses 7 unit delay cell, the Vernier Delay Line is used each delay cell. So proposed Time-to-Digital Converter uses total 21 phases. This Time-to-Digital Converter circuit is designed and laid out in $0.13{\mu}m$ 1P-6M CMOS technology. The proposed Time-to-Digital Converter achieves 26ps resolution, maximum input signal frequency is 100MHz and the digital output of proposed Time-to-Digital Converter are 8-bits. The proposed TDC detect 5ns phase difference between Start and Stop signal. A power consumption is 8.4~12.7mW depending on Enable signal width.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.7
• /
• pp.1442-1447
• /
• 2004

In this paper, a 6-Bit CMOS Folding and Interpolating AD Converter is presented. The converter is considered to be useful as an integrated part of a VLSI circuit handling both analog and digital signals as in the case of HDD or LAN applications. A built-in analog circuit for VLSI of a high-speed data communication requires a small chip area, low power consumption, and fast data processing. The proposed folding and interpolating AD Converter uses a very small number of comparators and interpolation resistors, which is achieved by cascading a couple of folders working in different principles. This reduced number of parts is a big advantage for a built-in AD converter design. The design is based on 0.25m double-poly 2 metal n-well CMOS process. In the simulation, with the applied 2.5V and a sampling frequency of 500MHz, the measurements are as follows: power consumption of 27mw, INL and DNL of $\pm$0.1LSB, $\pm$0.15LSB each, SNDR of 42dB with an input signal of 10MHz.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.12
• /
• pp.2317-2325
• /
• 2016

This paper presents a 10 bit successive approximation register (SAR) analog-to-digital converter (ADC) with a reference driver. The proposed SAR ADC consists of a capacitive digital-to-analog converter (CDAC), a comparator, a SAR logic, and a reference driver which improves the immunity to the power supply noise. The reference driver generates the reference voltages of 0.45 V and 1.35 V for the SAR ADC with an input voltage range of ${\pm}0.9V$. The SAR ADC is implemented using a $0.18-{\mu}m$ CMOS technology with a 1.8-V supply. The proposed SAR ADC including the reference driver almost maintains an input voltage range to be ${\pm}0.9V$ although the variation of supply voltage is +/- 200 mV. It consumes 5.32 mW at a sampling rate of 10 MS/s. The measured ENOB, DNL, and INL of the ADC are 9.11 bit, +0.60/-0.74 LSB, and +0.69/-0.65 LSB, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2006.05a
• /
• pp.607-610
• /
• 2006

The Digital Frequency Synthesizer(DFS) that generates the wideband signal with hish speed frequency hopping rate and high frequency resolution characteristics was implemented in this paper. The DFS was applied as local oscillator for direct frequency conversion IF modules of DVB-RCS, which directly generates the transmission immediate frequency signal by using DDS and wideband PLL technologies. The DDS technology provides high speed frequency hopping rate and high frequency resolution characteristics, which ate also the DVB-RCS requirement. The wideband PLL technology also provides the wideband signal generation, which is a necessity for direct frequency conversion modules. The implemented DFS provide the spurious suppression characteristic of -50 dBc, frequency resolution of 0.233 Hz and frequency hopping rate of 125 ns, respectively. Also the DFS represent the amplitude flatness of 3 dB and less in the pass-band and phase noise characteristic of -75 dBc/Hz at 1 kHz frequency offset.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.2
• /
• pp.223-228
• /
• 2007

The Digital Frequency Synthesizer(DFS) that generates the wideband signal with high speed frequency hopping rate and high frequency resolution characteristics was designed and implemented in this paper The DFS was applied as local oscillator for direct frequency conversion IF modules of DVB-RCS, which directly generates the transmission immediate frequency signal by using DDS and wideband PLL technologies. The DDS technology provides high speed frequency hopping rate and high frequency resolution characteristics, which are also the DVB-RCS requirement. The wideband PLL technology also provides the wideband signal generation, which is a necessity for direct frequency conversion modules. The implemented DFS provides the spurious suppression characteristic of -50 dBc and less, frequency resolution of 0.233 Hz and frequency hopping rate of 125 ns, respectively. Also the DFS represents the amplitude flatness of 3 dB and less in the pass-band, and phase noise characteristic of -75 dBc/Hz at 1 kHz frequency offset.

• Journal of Broadcast Engineering
• /
• v.21 no.5
• /
• pp.803-815
• /
• 2016

In this paper, we design a direct radio frequency (RF) sampling receiver for multiband GNSS signals and demonstrate its performance. The direct RF sampling is a technique that does not use an analog mixer, but samples the passband signal directly, and all receiver processes are done in digital domain, whereas the conventional intermediate frequency (IF) receiver samples the IF band signals. In contrast to the IF sampling receiver, the RF sampling receiver is less complex in hardware, reconfigurable, and simultaneously converts multiband signals to digital signals with an analog-to-digital (AD) converter. The reconfigurability and simultaneous reception are very important in military applications where rapid change to other system is needed when a system is jammed by an enemy. For simultaneous reception of multiband signals, the sampling frequency should be selected with caution by considering the carrier frequencies, bandwidths, desired intermediate frequencies, and guard bands. In this paper, we select a sampling frequency and design a direct RF sampling receiver to receive multiband global navigation satellite system (GNSS) signals such as GPS L1, GLONASS G1 and G2 signals. The receiver is implemented with a commercial AD converter and software. The receiver performance is demonstrated by receiving the real signals.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.11
• /
• pp.149-156
• /
• 2012

A digital input class-D audio amplifier is presented for digital hearing aid. The class-D audio amplifier is composed of digital and analog circuits. The analog circuit converts a digital input to a analog audio signal (DAC) with noise suppression in the audio band. An interpolated digital delta-sigma modulator is used to convert data types between digital signal processor (DSP) and digital-to-analog converter (DAC). An 16-bit, 25-kbps pulse code modulated (PCM) input is interpolated to 16-bit, 50-kbps by a digital filter. The output signal of interpolation filter is noise-shaped by a third-order digital sigma-delta modulator (SDM). As a result, 1.5-bit, 3.2-Mbps signal is applied to simple digital to analog converter.