• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.190-192
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• 2018

This paper describes a design of an elliptic curve cryptography (ECC) processor that supports five pseudo-random curves and five Koblitz curves over binary field defined by the NIST standard. The ECC processor adopts the Lopez-Dahab projective coordinate system so that scalar multiplication is computed with modular multiplier and XORs. A word-based Montgomery multiplier of $32-b{\times}32-b$ was designed to implement ECCs of various key lengths using fixed-size hardware. The hardware operation of the ECC processor was verified by FPGA implementation. The ECC processor synthesized using a 0.18-um CMOS cell library occupies 10,674 gate equivalents (GEs) and 9 Kbits RAM at 100 MHz, and the estimated maximum clock frequency is 154 MHz.

• Aerospace Engineering and Technology
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• v.12 no.1
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• pp.46-53
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• 2013

In this study, the analysis of electromagnetic environment of goheung aviation center was performed. If the test object has restrictions to be tested in indoor test facility, open area test site can be used to perform EMC test. Open area test site shall have no obstacles that can generate or reflect the electric field so as to prevent the measurement result from being influenced by unnecessary field. Goheung aviation center is surrounded by fields, and has no buildings that can reflect electric field, so the center can be a good candidate for open area test site. Ambient noise at Goheung aviation center was measured, and the result show that the center has good electromagnetic environment to perform EMC test for large volume object.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.875-878
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• 2015

In this paper, we propose an intra prediction hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC encoder. The proposed intra prediction hardware architecture uses common operation units to reduce computational complexity and uses $4{\times}4$ block unit to reduce hardware area. In order to reduce operation time, common operation unit uses one operation unit to generate predicted pixels and filtered pixels in all prediction modes. Intra prediction hardware architecture introduces the $4{\times}4$ PU design processing to reduce the hardware area and uses intemal registers to support $32{\times}32$ PU processmg. The proposed hardware architecture uses ten common operation units which can reduce execution cycles of intra prediction. The proposed Intra prediction hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 41.5k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 150MHz, it can support 4K UHD video encoding at 30fps in real time, and operates at a maximum of 200MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.2A
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• pp.80-85
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• 2003

This paper proposes Galois Field Arithmetic Unit(GFAU) whose structure does addition, multiplication and division in GF(2m). GFAU can execute maximum two additions, or two multiplications, or one addition and one multiplication. The base architecture of this GFAU is a divider based on modified Euclid's algorithm. The divider was modified to enable multiplication and addition, and the modified divider with the control logic became GFAU. The GFAU for GF(2193) was implemented with Verilog HDL with top-down methodology, and it was improved and verified by a cycle-based simulator written in C-language. The verified model was synthesized with Samsung 0.35um, 3.3V CMOS standard cell library, and it operates at 104.7MHz in the worst case of 3.0V, 85$^{\circ}C$, and it has about 25,889 gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11C
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• pp.1541-1550
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• 2004

In this paper, we propose an advanced hardware architecture for fast multi-resolution motion estimation of the video coding standard MPEG-1,2 and MPEG-4 AVC. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and fast operation by using the shared memory, the special ram architecture, the motion vector for 4 pixel x 4 pixel, the spiral search and so on. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur Altera FPGA and also by ASIC synthesis using Samsung 0.18 m CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 140 MHz, processing more than 1,100 QCIF video frames or 70 4CIF video frames per second. The hardware is going to be used as a core module when implementing a complete MPEG-4 AVC video encoder ASIC for real-time multimedia application.

• Journal of Korea Multimedia Society
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• v.15 no.1
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• pp.81-86
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• 2012

This paper presents a VLSI design for lifting-based discrete wavelet transform (DWT) 9/7 filter using multiplierless multiple constant multiplication (MCM) architecture. This proposed design is based on the lifting scheme using pattern search for folded architecture. Shift-add operation is adopted to optimize the multiplication process. The conventional serial operations of the lifting data flow can be optimized into parallel ones by employing paralleling and pipelining techniques. This optimized design has simple hardware architecture and requires less computation without performance degradation. Furthermore, hardware utilization reaches 100%, and the number of registers required is significantly reduced. To compare our work with previous methods, we implemented the architecture using Verilog HDL. We also executed simulation based on the logic synthesis using $0.18{\mu}m$ CMOS standard cells. The proposed architecture shows hardware reduction of up to 60.1% and 44.1% respectively at 200 MHz clock compared to previous works. This implementation results indicate that the proposed design performs efficiently in hardware cost, area, and power consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.68-73
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• 2009

This paper presents an easily modifiable structure of a serial peripheral interface (SPI) that is suitable for efficient testing of CMOS RF integrated circuits. The proposed SPI Is designed so that the address size and the accompanying software can be easily adjusted and modified according to the requirements and complexity of RF IC's under development. The hardware architecture and software algorithm to achieve the flexibility are described. The proposed SPI is fabricated in $0.13{\mu}m$ CMOS and successfully verified experimentally with a 2.7GHz fractional-N delta-sigma frequency synthesizer as a device under test.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.103-109
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• 2007

This paper presents behavioral models using SIMULINK and Verilog-a for a PLL based fractional-N frequency synthesizer. By adopting a top-down approach along with the traditional bottom-up transistor level design in parallel, the design time is greatly shortened, and a co-verification method for both the digital and the analog part is considered. Under this consideration, the SIMULINK modeling reduces simulation time and easily estimates the PLL's performance on the top level. Verilog-a is able to verify the feasibility of each blocks at first hand because it is compatible with transister level circuits. Then, an efficient way of the design is presented by comparing the results of both models.

• The Journal of the Acoustical Society of Korea
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• v.13 no.2
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• pp.30-37
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• 1994

Since the morden targets are of high speed and getting quiet in both active and passive mode, the necessities of developing advanced SONAR system capable of performing target motion analysis (TMA) and target classification are evident. In order to develop such a system, the scattering mechanism of complex bodies needs to be, some extent, fully understood and modeled. In this paper, MOving Spread Target(MOST) signal simulation model is presented and discussed. The model is based on the highlight distribution method, and simulates pulse elongation of spread target, doppler effect due to kinematics of the target as well as SONAR platform, and distribution target strength of each highlight point (HL) with directivity. The model can be used in developing and evaluating advanced SONAR system through system simulation, and can also be used in the development of target state estimation algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.4
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• pp.668-675
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• 2001

Recently, the performance of the commercial PCS(Personal Communication Service) system has been improved to the uppermost limit and ultimately the next generation mobile communication is to be realized by IMT-2000 (International Mobile Communication-2000) to provide multimedia services. Therefore, the new type receiving system is researched actively and one of the most important part in a receiver is direct conversion method. The direct conversion method is suitable for low power consumption, small size, MMIC, and low price, which is to be adopted to the next generation mobile communication systems. In this case, however, several problems occur due to DC-offset. The DC-offset suppresses amplification of the required signal because of the leakage signal of frequency synthesizer in the system. In this thesis, the removing method of DC-offset was considered. There are four removing techniques of DC-offset, which are AC-coupling, large capacitor, DC-feedback loop, and DC-free coding. Among these, the AC-coupling method is the most simplest method and the DC-feedback loop method has the best performance. Then, the performance of the AC-coupling method and DC-feedback loop method are evaluated by HP's ADS simulation tool. As a result, the AC-coupling method cannot be used to the digital communication systems due to data loss. On the other hand, it was confirmed that the DC-feedback loop method is suitable for the direct conversion receiver.