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Design of a GFAU(Galois Field Arithmetic Unit) in  

Kim, Moon-Gyung (연세대학교 전기전자공학화 Processor 연구실)
Lee, Yong-Surk (연세대학교 전기전자공학화 Processor 연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.28, no.2A, 2003 , pp. 80-85 More about this Journal
Abstract
This paper proposes Galois Field Arithmetic Unit(GFAU) whose structure does addition, multiplication and division in GF(2m). GFAU can execute maximum two additions, or two multiplications, or one addition and one multiplication. The base architecture of this GFAU is a divider based on modified Euclid's algorithm. The divider was modified to enable multiplication and addition, and the modified divider with the control logic became GFAU. The GFAU for GF(2193) was implemented with Verilog HDL with top-down methodology, and it was improved and verified by a cycle-based simulator written in C-language. The verified model was synthesized with Samsung 0.35um, 3.3V CMOS standard cell library, and it operates at 104.7MHz in the worst case of 3.0V, 85$^{\circ}C$, and it has about 25,889 gates.
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