• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.609-612
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• 2009

VHF helical antenna with sleeve is vary effective for reduce hand effect, but usually helical antenna has a small bandwidth. It is not sufficient for receive and transmission of signals. The paper deals with the application of these helical antenna. And we propose the design of frequency switching circuit for using helical antenna with sleeve.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.89-94
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• 2022

In this paper, a discrete-time loop filter(DLF) phase-locked loop with a Frequency Fluctuation Converting Circuit(FFCC) has been proposed. Discrete-time loop filter can improve spur characteristic by connecting the charge pump and voltage oscillator discretely unlike a conventional continuous-time loop filter. The proposed PLL is designed to operate stably by the internal negative feedback loop including the SSC acting as a negative feedback to the discrete-time loop filter of the external negative feedback loop. In addition, the phase noise is further improved by reducing the magnitude of the loop filter output voltage variation through the FFCC. Therefore, the magnitude of jitter has been reduced by 1/3 compared to the conventional structure. The proposed phase locked loop has been simulated with Hspice using the 1.8V 180nm CMOS process.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.4
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• pp.18-26
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• 2001

In this paper, we propose an ATC(Automatic Transfer mode Controller) algorithm and an average-mode-change method for use in Gear shift PLL which can automatically change loop gain. The proposed ATC algorithm accurately detects proper timing or the mode change and has a very simpler structure - than the conventional lock detector algorithm often used in QPSK. And the proposed average mode change method can obtain low errors of estimated frequency offset by averaging the loop filter output of frequency component in shift register. These algorithms are also useful in designing ASIC, since these algorithms occupy small circuit area and are adaptable for high speed digital processing. We also present phase tracking performance of proposed Gear-shift PLL, which is composed of polarity decision PD, ATC and average mode change circuit, and analyze the results by examining constellation at each mode.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.05a
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• pp.258-264
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• 1998

본문에서 주파수hopping과 이동통신에서 요구되는 고속 주파수 전환이 가능한 새로운 주파수 신시사이저 (Synthesizer)를 제안한다. 종래의 PLL 주파수 신시사이저는 기준 주파수와 출력의 채널 주파수 간격이 동일하기 때문에 기준 주파수를 낮게 하면 매우 긴 동기 시간이 소요된다. 본 논문에서 제안하는 주파수 신시사이저는 새로운 제어 방법을 이용한 다단 펄스 제거 회로를 사용하여 기준 주파수와 채널 간격 주파수를 독립적으로 설정할 수 있기 때문에 종래의 신시사이저와 동일한 채널 간격의 주파수를 유지시키면서 기준 주파수를 높일 수 있고, 또한 루프(loop)이득을 크게 할 수 있다. 따라서 종래의 주파수 신시사이저보다 주파수 절환시간을 크게 단축할 수 있다. 본 논문에서는 주파수 절환시간을 1/100 정도 단축시킬 수 있음을 보여주고 있다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.6
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• pp.51-57
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• 2017

In this paper, we designed a frequency synthesizer using DDS (Direct Digital Synthesizer) for Ka-band compact Radar. DDS is applied to generate various waveform and to cover high-speed frequency sweep. In order to reduce size, waveform generator and Ka band frequency up-converter are integrated in one module. Proposed frequency synthesizer provides LFM(Linear Frequency Modulation) waveform and Phase modulated FMCW (Frequency Modulation Continuous Wave) waveform. It is observed that fabricated synthesizer performs $0.191{\mu}sec$ frequency switching time and -89.16 dBc/Hz phase noise at offset 1 kHz.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.11 no.3
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• pp.106-113
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• 1997

In uninterruptible power supply(UPS), a high speed phase control is usually required to compensate transients in the output voltage at the instant of transfer from the ac line to the inverter when the ac line fails or backs to the ac line in case of the inverter fails. To overcome this problem, this paper pre¬sents the closed digital phase-locked loop(DPLL) techniques designed by full software with TMS320C31 digital signal processor and describes the functional operation of the proposed DPLL. Fi¬nally, the performance of the proposed DPLL is shown and discussed through simulation and experiment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.269-270
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• 2006

이 논문에서는 고온초전도체로 제작된 위성통신용 고온초전도 3dB 커플러에 대하여 보고한다. 커플러 제작에 사용된 초전도체는 MgO 기판위에 증착된 YBCO 고온초전도 박막이었다. 중심 주파수는 408 MHz 대역폭은 위성통신 기지국용 전력 결합기가 안정적으로 동작하도록 15 MHz의 광대역을 설정하였다. 설계를 위해 기존의 분포정수로회로를 ABCD Matrix를 이용해서 집중정수 회로로 전환하였고, 컴퓨터 모의실험을 위해 em Sonnet 상업용 프로그램을 사용하였다. 컴퓨터 모의 실험시 초전도체의 저항은 0으로 하였고, 기타 유전손실은 없는 것으로 가정하였다. 측정결과 우수한 대역폭 특성을 보여주었지만, 대체적으로 12 MHz의 대역폭이 측정되었으며 이는 설계시 모멘트 법 적용에 따른 계산 셀의 정밀도에서 기인하는 것으로 보이며 좀더 세밀한 계산 셀을 사용할 경우, 정확한 계산이 가능할 것으로 판단된다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.12
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• pp.1375-1382
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• 2008

Frequency adjustable D-CRLH(dual-composite right/left handed) transmission lines, which solve the problem of design complexity and uncontrolled frequency of the existing structures, are proposed in this paper. The first design(type I), consisting of defected ground structure(DGS), island pattern in DGS, fixed stub and varactor diodes, controls $C_L$ in the parallel resonant circuit, while the second structure(type 2) composed of fixed DGS, shunt stub and diode adjusts $C_R$ in the series resonant circuit. The dual band frequency points which correspond to the meaningful electrical length of +/-90 degree in the RH/LH region are adjustable according to the bias voltage. The measurement shows that the LH frequency point which has -90 degree of electrical length are adjusted over $4.22{\sim}5.39\;GHz$ and $4.21{\sim}5.05\;GHz$ for type 1 and type 2, respectively, under $1{\sim}12\;V$ of bias voltage. In addition, the frequency Woo where RH turns over LH is controled over $3.26{\sim}4.22\;GHz$ for type 2 with the same bias condition.

• The Journal of the Acoustical Society of Korea
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• v.25 no.1
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• pp.7-13
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• 2006

Fisheries policy change from catching to farming requires more intensive consideration for aquaculture industry. The oceanic farm is a desirable cost effective aquaculture method. However. in odor to gather fish in the oceanic farm, eating sound or any attracting sound should be radiated through underwater loudspeaker. In this Paper, it has been found in literature that the frequency range responding to fish is about 16Hz to 13kHz but sensitive frequency range is about 150Hz to 2kHz and sound pressure level is about 100dB to 150dB reference $1{\mu}Pa$. Therefore, frequency range and output sound level of designed underwater loudspeaker has been specified as 150Hz to 3kHz and 100dB to 145dB reference $1{\mu}bar$. respectively To verify the stability and the endurance to the pressure of 40m water depth, manufactured underwater loudspeaker was examined before sea trial in manufactured water pressure tank which gives a maximum of 10 atmospheric Pressure. We experimented on acoustic characteristic with manufactured underwater loudspeaker under water depth of 10m.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.4
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• pp.864-870
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• 2017

This paper describes a Dual Buck Converter with mode control using variable Frequency to Voltage for portable devices requiring wide load current. The inherent problems of PLL compensation and efficiency degradation in light load current that the conventional hysteretic buck converter has faced have been resolved by using the proposed Dual buck converter which include improved PFM Mode not to require compensation. The proposed mode controller can also improve the difficulty of detecting the load change of the mode controller, which is the main circuit of the conventional dual mode buck converter, and the slow mode switching speed. the proposed mode controller has mode switching time of at least 1.5us. The proposed DC-DC buck converter was implemented by using $0.18{\mu}m$ CMOS process and die size was $1.38mm{\times}1.37mm$. The post simulation results with inductor and capacitor including parasitic elements showed that the proposed circuit received the input of 2.7~3.3V and generated output of 1.2V with the output ripple voltage had the PFM mode of 65mV and 16mV at the fixed switching frequency of 2MHz in hysteretic mode under load currents of 1~500mA. The maximum efficiency of the proposed dual-mode buck converter is 95% at 80mA and is more than 85% efficient under load currents of 1~500mA.