• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.152-162
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• 2003

In this paper, Binary to Quaternary Converter(BQC), Quaternary to Binary Converter(QBC) and Quaternary inverter circuit, which is the basic logic gate, have been proposed based on voltage mode. The BQC converts the two bit input binary signals to one digit quaternary output signal. The QBC converts the one digit quaternary input signal to two bit binary output signals. And two circuits consist of Down-literal circuit(DLC) and combinational logic block(CLC). In the implementation of quaternary inverter circuit, DLC is used for reference voltage generation and control signal, only switch part is implemented with conventional MOS transistors. The proposed circuits are simulated in 0.35 ${\mu}{\textrm}{m}$ N-well doubly-poly four-metal CMOS technology with a single +3V supply voltage. Simulation results of these circuit show 250MHz sampling rate, 0.6mW power consumption and maintain output voltage level in 0.1V.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.123-131
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• 2002

In this paper, a new standard basis parallel ternary-valued multiplier circuit designed using current mode CMOS is presented. Prior to constructing the GF(3$^{ｍ}$) multiplier circuit, we provide a GF(3) adder and a GF(3) multiplier with truth tables and symbolize them, and also design them using current mode CMOS circuit. Using the basic ternary operation concept, a ternary adder and a multiplier, we develop the equations to multiply arbitrary two elements over GF(3$^{ｍ}$). Following these equations, we can design a multiplier generalized to GF(3$^{ｍ}$). For the proposed circuit in this paper, we show the example in GF(3$^{3}$). In this paper, we assemble the operation blocks into a complete GF(3$^{ｍ}$) multiplier. Therefore the proposed circuit is easy to generalize for m and advantageous for VLSI. Also, it need no memory element and the latency not less fewer than other circuit. We verify the proposed circuit by functional simulation and show its result.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.11
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• pp.144-151
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• 1998

In this paper, it is applied the analysis properties of mathematical morphology in order to process MIN/MAX operation on the basis of combination of predefined and weighted structuring element to FCNN having the structure of CNN combined with fuzzy logic between template and input/output. In this paper, as the fuzzy estimator is applied to the image including noise, thus it could be found the noise removal as well as the edge detection in the process of computer simulation. We could analyze and compare the results of edge detection using FCNN, CNN and median filter to which the erosion operation of morphology is applied. This paper could apply the static template and the variable template to FCNN using the quantization fuzzy function, in result we could confirm that the performance of FCNN got to improve in the process of computer simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.82-88
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• 2007

In this paper, we present a pattern comparison algorithm for reducing fault candidate lists. The number of fault candidates determines the total fault simulation time. To decrease the total fault diagnosis time, the reduction of the number of fault candidates is essential. Critical path tracing determines fault candidate lists detected by a set of tests using a backtracing algorithm starting at the primary outputs of a circuit. The proposed algorithm reduces fault candidates comparing failing patterns with good patterns during critical path tracing process. As we reduce all fault candidates of the circuit to more accurately suspected fault candidates, we can greatly reduce fault simulation time. The proposed algorithm greatly increases simulation speed than that of a conventional backtracing method. The proposed algorithm is applicable to both combinational and sequential circuits. Experimental results on ISCAS#85 and ISCAS#89 benchmark circuits showed fault candidates are pruned and fault diagnosis time is also decreased in proportion to fault candidate decrease.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1739-1752
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• 1996

Software reengineering involves improving the software maintenance process and improving existing systems by applying new technologies and software tools. Software reengineering can help us understand existing systems and discover software components that are common across systems. In the paper, we discuss the program analysis and environment to assist reengineering. Program analysis takesan existing program as input and generates information about structured part and object-oriented part. It is used to restructure the information by extracting code through reengineering methodology. These restructuring informations with object-oriented archilccture are mapping prolog form to query by using direct reation and summary relation.

• Archives of design research
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• v.14 no.4
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• pp.99-108
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• 2001

The Charm is composed of various kind of ancient signs, letters and systematic characters so that they delivers messages with many expressions. They, compared with the experimental typography, are more logical and experimental than we generally think. Also, they have meanings and attributes as characters do, in which there are symbols, hieroglyphs, pictures and other similar words. Each attribute diverse from symbolic meaning, associates to deconstruction of letters. It is needed to review the experimental attributes of charms with the view of structural typography for potentialities of expression. The purpose of the study is to analyze and classify the morphologic construction of charms so that we can find the possibilities of applying the attributes to visual languages and typography. Future study seems to be extending the area of expressing of typography fit for our own culture, not for Western

• The Journal of Korean Association of Computer Education
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• v.3 no.2
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• pp.87-94
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• 2000

Software productivity doesn't satisfy the need of service of software users and software quality isn't improved. Moreover, we still have difficulty in software maintenance. As a plan to counteract solving this crisis, the technology that is called CBSE or Componentware is introduced. Componet Based Software Architecture, one of the technologies associated with CBSE, as a structural description of system, describes both the components composed system of and interaction among these components. Software Architecture provides the technology and the methodology of composition among components in the field of CBSE. is accepted one of core technologies. In this thesis, we analyse information necessary for component specification and then proposed that component specificaton activities using formal specification language Z which is verified with the ability of analysis and logicality. The proposed activities are composed of 9 tasks. By presenting specific 11 products, it is also proposed that component specification activities which is the base of CBSD(ComponentBased Software Development) for reusing.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.7
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• pp.8-17
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• 2010

Ubiquitous home refers not only to home but also to logical space, including a wide range of out-home personal devices such as mobile phones, PDAs, laptops, car navigators, and office PCs. There are certain connection barriers among the devices, such as the dynamic IP address, NAT. In a home network, various devices coexist in heterogeneous networks, such as IP, IEEE1394, PLC, Bluetooth, ZigBee, UWB, and IrDA, all of which lack interoperability due to their different physical transmission characteristics and protocols. In ubiquitous home where an unrestricted collaboration of the devices is essential to offer services that meet the users' requirements, free interoperability among the devices must be guaranteed. This paper proposes a networking model for interoperability of the heterogeneous devices in a ubiquitous home based on a virtual overlay network which hides the complicated physical network configurations and heterogeneity of the service protocols.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.85-92
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• 2009

This paper proposes a full-search block-matching motion estimation circuit with hybrid architecture combining systolic arrays and adder trees for an MPEG-4 encoder. The proposed circuit uses systolic arrays for motion estimation with a small number of clock cycles and adder trees to reduce required circuit resources. The interpolation circuit for 1/2 pixel motion estimation consists of six adders, four subtracters and ten registers. We improved the circuit performance by resource sharing and efficient scheduling techniques. We described the motion estimation circuit for integer and 1/2 pixels at RTL in Verilog HDL. The logic-level circuit synthesized by using 130nm standard cell library contains 218,257 gates and can process 94 D1($720{\times}480$) image frames per second.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.50-57
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• 2000

We propose a logic synthesis algorithm for the design of FPGAs operating at high speed. FPGA is a novel technology that provides programmability in the field. Because of short turnaround time and low manufacturing cost, FPGA has been noticed as an ideal device for system prototyping. Despite these merits, FPGA has drawbacks, namely low integration and long delay time comparing to ASIC. The proposed algorithm partitions a given circuit into subcircuits utilizing a kernel divisor such that the subcircuits can be performed at the same time, hence reducing the delay of the circuit. Experimental results on the MCNC benchmark show that the proposed algorithm is effective by generating circuits having 19.1% les delay on average, when compared to the FlowMap algorithm.