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Full-Search Block-Matching Motion Estimation Circuit with Hybrid Architecture for MPEG-4 Encoder  

Shim, Jae-Oh (Department of Electronics and Information Engineering, Hankuk University of Foreign Studies)
Lee, Seon-Young (Department of Electronics and Information Engineering, Hankuk University of Foreign Studies)
Cho, Kyeong-Soon (Department of Electronics and Information Engineering, Hankuk University of Foreign Studies)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.2, 2009 , pp. 85-92 More about this Journal
Abstract
This paper proposes a full-search block-matching motion estimation circuit with hybrid architecture combining systolic arrays and adder trees for an MPEG-4 encoder. The proposed circuit uses systolic arrays for motion estimation with a small number of clock cycles and adder trees to reduce required circuit resources. The interpolation circuit for 1/2 pixel motion estimation consists of six adders, four subtracters and ten registers. We improved the circuit performance by resource sharing and efficient scheduling techniques. We described the motion estimation circuit for integer and 1/2 pixels at RTL in Verilog HDL. The logic-level circuit synthesized by using 130nm standard cell library contains 218,257 gates and can process 94 D1($720{\times}480$) image frames per second.
Keywords
MPEG-4 인코더;움직임 추정;전역 탐색 블록 정합 알고리즘;보간;
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