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(The Design of Parallel Ternary-Valued Multiplier Using Current Mode CMOS)  

Sim, Jae-Hwan (Dept.of Electronics Engineering, Inha University)
Byeon, Gi-Yeong (Dept.of Electronics Engineering, Inha University)
Yun, Byeong-Hui (Dept.of Electronics Engineering, Inha University)
Lee, Sang-Mok (Dept.of Electronics Engineering, Inha University)
Kim, Heung-Su (Dept.of Electronics Engineering, Inha University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.39, no.2, 2002 , pp. 123-131 More about this Journal
Abstract
In this paper, a new standard basis parallel ternary-valued multiplier circuit designed using current mode CMOS is presented. Prior to constructing the GF(3$^{ｍ}$) multiplier circuit, we provide a GF(3) adder and a GF(3) multiplier with truth tables and symbolize them, and also design them using current mode CMOS circuit. Using the basic ternary operation concept, a ternary adder and a multiplier, we develop the equations to multiply arbitrary two elements over GF(3$^{ｍ}$). Following these equations, we can design a multiplier generalized to GF(3$^{ｍ}$). For the proposed circuit in this paper, we show the example in GF(3$^{3}$). In this paper, we assemble the operation blocks into a complete GF(3$^{ｍ}$) multiplier. Therefore the proposed circuit is easy to generalize for m and advantageous for VLSI. Also, it need no memory element and the latency not less fewer than other circuit. We verify the proposed circuit by functional simulation and show its result.
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