Browse > Article

A Pattern Comparison Algorithm for Pruning Fault Candidates  

Cho, Hyung-Jun (Department of Electrical Electronic Engineering, Yonsei University)
Kang, Sung-Ho (Department of Electrical Electronic Engineering, Yonsei University)
Publication Information
Abstract
In this paper, we present a pattern comparison algorithm for reducing fault candidate lists. The number of fault candidates determines the total fault simulation time. To decrease the total fault diagnosis time, the reduction of the number of fault candidates is essential. Critical path tracing determines fault candidate lists detected by a set of tests using a backtracing algorithm starting at the primary outputs of a circuit. The proposed algorithm reduces fault candidates comparing failing patterns with good patterns during critical path tracing process. As we reduce all fault candidates of the circuit to more accurately suspected fault candidates, we can greatly reduce fault simulation time. The proposed algorithm greatly increases simulation speed than that of a conventional backtracing method. The proposed algorithm is applicable to both combinational and sequential circuits. Experimental results on ISCAS#85 and ISCAS#89 benchmark circuits showed fault candidates are pruned and fault diagnosis time is also decreased in proportion to fault candidate decrease.
Keywords
Diagnosis; Critical path tracing; Fault simulation; Pattern comparison; Candidate;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Marzouki, J. Laurent and B. Courtois, 'Coupling Electron-Beam Probing with Knowledge-Based Fault Localization', Proc. of International Test Conference, pp. 238-247, 1991
2 S. Venkataraman and S. Drummonds, 'Poirot : Applications of a Logic Fault Diagnosis Tool', IEEE Design & Test of Computers, pp. 19-30, 2001
3 Hyungjun Cho, Joohwan Lee, Yoseop Lim, Sungho Kang, 'An Effective fault diagnosis using critical path tracing', Proc. of Korea Test Conference, pp. 8-12, 2005
4 S. Venkataraman, Ismed Hartanto and W.K. Fuchs, 'Dynamic Diagnosis of Sequential Circuits Based on Stuck-at Faults', Proc. of VLSI Test Symposium, pp. 198-203, 1996
5 S. D. Millman, E. J. McCluskey and J. M. Acken, 'Diagnosing CMOS Bridging Faults with Stuck-At-Fault Dictionaries', Proc. of International Test Conference, pp. 860-870, 1990
6 Jiang Brandon Liu, 'Incremental Fault Diagnosis', IEEE Transactions on Computers, pp. 240-251, 2005
7 Joohwan Lee, Yoseop Lim, Hyungjun Cho, Sungho Kang, 'An Efficient matching Algorithm using the Number of Primary Outputs for Fault Diagnosis', Proc. of 2005 SOC Design Conference, pp. 295-298, 2005
8 Pomeranz and S. M. Reddy, 'On Dictionary- Based Fault Location in Digital Logic Circuits', IEEE Transactions on Computers, pp. 48-59, 1997
9 Abramovici, 'A Maximal Resolution Guided-Probe Testing Algorithm', Proc. of Design Automation Conference, pp. 189-195, 1989
10 Boppana V., Fujita M., 'Modeling the unknown! Towards model-independent fault and error diagnosis', Proc. of International Test Conference, pp. 1094-1101, 1998