• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.649-654
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• 2011

In this paper, we show new method to find number of errors in the Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square calculating circuit and parallel processing. The microcontroller of this Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

• Proceedings of the KSRS Conference
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• 2006.03a
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• pp.49-52
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• 2006

최근 대규모 지역 혹은 전 지구에 걸친 분석 및 모니터링을 위한 위성영상의 사용이 늘어나면서 이를 처리하기 위한 효율적인 '영상좌표 상호등록'법이 요구되고 있다. 이에 본 연구에서는 일반적으로 오랜 시간이 소요되는 '영상좌표 상호등록'의 효율성을 높이기 위해 '사전검수영역기반정합법'(Pre-qualified area based matching)을 사용하였다. 이를 통해 '영상좌표 상호등록'시 연산시간을 현저히 단축시켰고 추출된 정합점에 과대오차제거법을 적용함으로서 단순히 영역기반정합법을 적용한 경우에 비해서 정확도가 향상됨을 확인할 수 있었다. 제안한 알고리즘을 이용하여 테스트 프로그램을 작성, 한반도 Landsat ETM+ 영상 3장을 이용하여 테스트하였다. 정합점 간의 평균제곱오차는 0.436 영상소, 정합점은 평균 38,475개로 나타났다. 연산시 간은 평균 약 8분으로 나타났다.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04a
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• pp.275-277
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• 2003

본 논문에서는 GF(2$^{m}$ )상에서 비트 직렬 Linear Feedback Shift Register (LFSR) 구조와 비트 병렬 셀룰라 오토마타(Cellular Automata, CA)구조를 혼합한 새로운 하이브리드(Hybrid) 형식의 A$B^2$곱셈기를 제안한다. 본 논문에서 제안한 곱셈기는 제곱연산을 위해 구조적으로 가장 간단한 비트 직렬 구조를 이용하고, 곱셈연산을 위해 시간 지연이 적은 비트 병렬 구조를 이용한다. 제안된 구조는 LFSR의 구조적인 특징과 Periodic Boundary CA (PBCA)의 특성, 그리고 All One Polynomial (AOP)의 특성을 조화시킴으로써 기존의 구조에 비하여 정규성을 높이고 지연 시간을 줄일 수 있는 구조이다. 제안된 곱셈기는 공개키 암호화의 핵심이 되는 지수기의 구현을 위한 효율적인 기본구조로 사용될 것으로 기대된다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.406-409
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• 2007

This paper proposes an algorithm that predicts current electrostatic charge in a factory. The algorithm based on LSM(Least Square Method) dynamically takes the number of sample while calculating the value of electrostatic charge. The simulation results show that the proposed algorithm gains 73.18161 standard deviation with 95% trust probability and is better than conventional algorithm. We design the electrostatic prediction embedded system based on pxa255 with the proposes algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.80-86
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• 2003

Elliptic curve cryptosystem(ECC) offers the highest security per bit among the known publick key system. The benefit of smaller key size makes ECC particularly attractive for embedded applications since its implementation requires less memory and processing power. In this paper, we propose a new multiplier structure with configurable output sizes and operation cycles. The number of output bits can be freely chosen in the new architecture with the performance-area trade-off depending on the application. Using the architecture, a 193-bit normal basis multiplier and inversion unit are designed in GF(2$^{m}$ ). It is implemented using HDL and 0.35${\mu}{\textrm}{m}$ CMOS technology and the operation is verified by simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.37-42
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• 2008

In this paper, we propose a partial product addition method using variable groups in the design of operators such as multipliers and digital filters. By this method, full adders can be replaced with simple logic circuits. To show the efficiency of the proposed method, we applied the method to the design of squarers and precomputer blocks of FIR filters. In case of 7 bit and 8 bit squarers, it is shown that by the proposed method, area, power and delay time can be reduced up to {22.1%, 20.1%, 14%} and {24.7%, 24.4%, 6.7%}, respectively, compared with the conventional method. The proposed FIR precomputer circuit leads to up to {63.6%, 34.4%, 9.8%} reduction in area, power consumption and propagation delay compared with previous method.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.6
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• pp.63-70
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• 2009

Many research results show that RSA system mounted using conventional binary exponentiation algorithm is vulnerable to some physical attacks. Recently, Schmidt and Hurbst demonstrated experimentally that an attacker can exploit secret key using faulty signatures which are obtained by skipping the squaring operations. Based on similar assumption of Schmidt and Hurbst's fault attack, we proposed new fault analysis attacks which can be made by skipping the multiplication operations or computations in looping control statement. Furthermore, we applied our attack to Montgomery ladder exponentiation algorithm which was proposed to defeat simple power attack. As a result, our fault attack can extract secret key used in Montgomery ladder exponentiation.

• The Korean Journal of Applied Statistics
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• v.21 no.6
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• pp.901-910
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• 2008

Incidence of Plasmodium vivax malaria in South Korea have been reemerged from mid-1990 and infected around 1600 patients annually recent years. The authors calculated the distribution of malaria infection and prevalence in South Korea using incidence (2001-2006) and incubation period distributions by a back-calculation formula and the least squares estimation method. The estimated infection has a normal distribution with a mean 207 and a standard deviation 30.7 days. In addition, the authors found the estimated daily average prevalence is 628.8 patients.

• Journal of rehabilitation welfare engineering & assistive technology
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• v.11 no.4
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• pp.363-370
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• 2017

In this paper, we proposed a low-complexity speech enhancement algorithm based on a improved minima controlled recursive averaging (IMCRA) and log minimum mean square error (logMMSE). The IMCRA algorithm track the minima value of input power within buffers in local window and identify the speech presence using ratio between input power and its minima value. In this process, many number of operations are required. To reduce the number of operations of IMCRA algorithm, minima value is tracked using time-varying frequency-dependent smoothing based on speech presence probability. The proposed algorithm enhanced speech quality by 2.778%, 3.481%, 2.980% and 2.162% in 0, 5, 10 and 15dB SNR respectively and reduced computational complexity by average 9.570%.

• Journal of the Korea Society of Computer and Information
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• v.25 no.2
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• pp.41-48
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• 2020

In this paper, we derive a common computational part in an algorithm that can simultaneously perform multiplication and square over finite fields, and propose a low-area bit-parallel systolic array that reduces hardware through sequential processing. The proposed systolic array has less space and area-time (AT) complexity than the existing related arrays. In detail, the proposed systolic array saves about 48% and 44% of Choi-Lee and Kim-Kim's systolic arrays in terms of area complexity, and about 74% and 44% in AT complexity. Therefore, the proposed systolic array is suitable for VLSI implementation and can be applied as a basic component in hardware constrained environment such as IoT.